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-rw-r--r--fpga/usrp2/top/E1x0/.gitignore6
-rw-r--r--fpga/usrp2/top/E1x0/E1x0.ucf261
-rw-r--r--fpga/usrp2/top/E1x0/E1x0.v196
-rw-r--r--fpga/usrp2/top/E1x0/Makefile17
-rw-r--r--fpga/usrp2/top/E1x0/Makefile.E100106
-rw-r--r--fpga/usrp2/top/E1x0/Makefile.E110106
-rw-r--r--fpga/usrp2/top/E1x0/README4
-rw-r--r--fpga/usrp2/top/E1x0/cmdfile20
-rwxr-xr-xfpga/usrp2/top/E1x0/core_compile3
-rw-r--r--fpga/usrp2/top/E1x0/make.sim7
-rw-r--r--fpga/usrp2/top/E1x0/tb_u1e.v58
-rw-r--r--fpga/usrp2/top/E1x0/timing.ucf23
12 files changed, 807 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/.gitignore b/fpga/usrp2/top/E1x0/.gitignore
new file mode 100644
index 000000000..8d872713e
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/.gitignore
@@ -0,0 +1,6 @@
+*~
+build
+*.log
+*.cmd
+tb_u1e
+*.lxt
diff --git a/fpga/usrp2/top/E1x0/E1x0.ucf b/fpga/usrp2/top/E1x0/E1x0.ucf
new file mode 100644
index 000000000..278fc289a
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/E1x0.ucf
@@ -0,0 +1,261 @@
+
+NET "CLK_FPGA_P" LOC = "Y11" ;
+NET "CLK_FPGA_N" LOC = "Y10" ;
+
+## GPMC
+NET "EM_D<15>" LOC = "D13" ;
+NET "EM_D<14>" LOC = "D15" ;
+NET "EM_D<13>" LOC = "C16" ;
+NET "EM_D<12>" LOC = "B20" ;
+NET "EM_D<11>" LOC = "A19" ;
+NET "EM_D<10>" LOC = "A17" ;
+NET "EM_D<9>" LOC = "E15" ;
+NET "EM_D<8>" LOC = "F15" ;
+NET "EM_D<7>" LOC = "E16" ;
+NET "EM_D<6>" LOC = "F16" ;
+NET "EM_D<5>" LOC = "B17" ;
+NET "EM_D<4>" LOC = "C17" ;
+NET "EM_D<3>" LOC = "B19" ;
+NET "EM_D<2>" LOC = "D19" ;
+NET "EM_D<1>" LOC = "C19" ;
+NET "EM_D<0>" LOC = "A20" ;
+
+NET "EM_A<10>" LOC = "C14" ;
+NET "EM_A<9>" LOC = "C10" ;
+NET "EM_A<8>" LOC = "C5" ;
+NET "EM_A<7>" LOC = "A18" ;
+NET "EM_A<6>" LOC = "A15" ;
+NET "EM_A<5>" LOC = "A12" ;
+NET "EM_A<4>" LOC = "A10" ;
+NET "EM_A<3>" LOC = "E7" ;
+NET "EM_A<2>" LOC = "A7" ;
+NET "EM_A<1>" LOC = "C15" ;
+
+NET "EM_NCS6" LOC = "E17" ;
+NET "EM_NCS5" LOC = "E10" ;
+NET "EM_NCS4" LOC = "E6" ;
+#NET "EM_NCS1" LOC = "D18" ;
+#NET "EM_NCS0" LOC = "D17" ;
+
+NET "EM_CLK" LOC = "F11" ;
+NET "EM_WAIT0" LOC = "F14" ;
+NET "EM_NBE<1>" LOC = "D14" ;
+NET "EM_NBE<0>" LOC = "A13" ;
+NET "EM_NWE" LOC = "B13" ;
+NET "EM_NOE" LOC = "A14" ;
+#NET "EM_NADV_ALE" LOC = "B15" ;
+#NET "EM_NWP" LOC = "F13" ;
+
+## Overo GPIO
+NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug
+NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug
+NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug
+NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug
+NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug
+NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug
+NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug
+
+NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10
+NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186
+
+NET "overo_gpio144" LOC = "A5" ; # tx_have_space
+NET "overo_gpio145" LOC = "C7" ; # tx_underrun
+NET "overo_gpio146" LOC = "A6" ; # rx_have_data
+NET "overo_gpio147" LOC = "B6" ; # rx_overrun
+NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug
+NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug
+NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug
+
+## Overo UART
+NET "overo_txd1" LOC = "C6" ;
+NET "overo_rxd1" LOC = "D6" ;
+NET "fpga_txd1" LOC = "AB9" ;
+NET "fpga_rxd1" LOC = "AB8" ;
+
+## FTDI UART to USB converter
+NET "FPGA_TXD" LOC = "G19" ;
+NET "FPGA_RXD" LOC = "F20" ;
+
+#NET "SYSEN" LOC = "C11" ;
+
+## I2C
+NET "db_scl" LOC = "F19" ;
+NET "db_sda" LOC = "F18" ;
+
+## SPI
+### DBoard SPI
+NET "db_sclk_rx" LOC = "D21" ;
+NET "db_miso_rx" LOC = "D22" ;
+NET "db_mosi_rx" LOC = "D20" ;
+NET "db_sen_rx" LOC = "E19" ;
+NET "db_sclk_tx" LOC = "F21" ;
+NET "db_miso_tx" LOC = "E20" ;
+NET "db_mosi_tx" LOC = "G17" ;
+NET "db_sen_tx" LOC = "G18" ;
+
+### AD9862 SPI and aux SPI Interfaces
+#NET "aux_sdi_codec" LOC = "G3" ;
+#NET "aux_sdo_codec" LOC = "F3" ;
+#NET "aux_sclk_codec" LOC = "C1" ;
+NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33;
+NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33;
+NET "miso_codec" LOC = "H4" ;
+NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33;
+
+### Clock Gen SPI
+NET "cgen_miso" LOC = "F22" ;
+NET "cgen_mosi" LOC = "E22" ;
+NET "cgen_sclk" LOC = "J19" ;
+NET "cgen_sen_b" LOC = "H20" ;
+
+## Clock gen control
+NET "cgen_st_status" LOC = "P20" ;
+NET "cgen_st_ld" LOC = "R17" ;
+NET "cgen_st_refmon" LOC = "P17" ;
+NET "cgen_sync_b" LOC = "U18" ;
+NET "cgen_ref_sel" LOC = "U19" ;
+
+## Debug pins
+NET "debug_led<3>" LOC = "Y15" ;
+NET "debug_led<2>" LOC = "K16" ;
+NET "debug_led<1>" LOC = "J17" ;
+NET "debug_led<0>" LOC = "H22" ;
+NET "debug<0>" LOC = "G22" ;
+NET "debug<1>" LOC = "H17" ;
+NET "debug<2>" LOC = "H18" ;
+NET "debug<3>" LOC = "K20" ;
+NET "debug<4>" LOC = "J20" ;
+NET "debug<5>" LOC = "K19" ;
+NET "debug<6>" LOC = "K18" ;
+NET "debug<7>" LOC = "L22" ;
+NET "debug<8>" LOC = "K22" ;
+NET "debug<9>" LOC = "N22" ;
+NET "debug<10>" LOC = "M22" ;
+NET "debug<11>" LOC = "N20" ;
+NET "debug<12>" LOC = "N19" ;
+NET "debug<13>" LOC = "R22" ;
+NET "debug<14>" LOC = "P22" ;
+NET "debug<15>" LOC = "N17" ;
+NET "debug<16>" LOC = "P16" ;
+NET "debug<17>" LOC = "U22" ;
+NET "debug<18>" LOC = "P19" ;
+NET "debug<19>" LOC = "R18" ;
+NET "debug<20>" LOC = "U20" ;
+NET "debug<21>" LOC = "T20" ;
+NET "debug<22>" LOC = "R19" ;
+NET "debug<23>" LOC = "R20" ;
+NET "debug<24>" LOC = "W22" ;
+NET "debug<25>" LOC = "Y22" ;
+NET "debug<26>" LOC = "T18" ;
+NET "debug<27>" LOC = "T17" ;
+NET "debug<28>" LOC = "W19" ;
+NET "debug<29>" LOC = "V20" ;
+NET "debug<30>" LOC = "Y21" ;
+NET "debug<31>" LOC = "AA22" ;
+NET "debug_clk<0>" LOC = "N18" ;
+NET "debug_clk<1>" LOC = "M17" ;
+
+NET "debug_pb" LOC = "C22" ;
+
+#NET "reset_codec" LOC = "C2" ;
+
+NET "RXSYNC" LOC = "F2" ;
+NET "DB<11>" LOC = "G6" ;
+NET "DB<10>" LOC = "G5" ;
+NET "DB<9>" LOC = "E4" ;
+NET "DB<8>" LOC = "E3" ;
+NET "DB<7>" LOC = "H6" ;
+NET "DB<6>" LOC = "H5" ;
+NET "DB<5>" LOC = "H1" ;
+NET "DB<4>" LOC = "G1" ;
+NET "DB<3>" LOC = "K5" ;
+NET "DB<2>" LOC = "K4" ;
+NET "DB<1>" LOC = "H2" ;
+NET "DB<0>" LOC = "L5" ;
+
+NET "DA<11>" LOC = "K6" ;
+NET "DA<10>" LOC = "K3" ;
+NET "DA<9>" LOC = "K2" ;
+NET "DA<8>" LOC = "N1" ;
+NET "DA<7>" LOC = "N5" ;
+NET "DA<6>" LOC = "N6" ;
+NET "DA<5>" LOC = "P2" ;
+NET "DA<4>" LOC = "P1" ;
+NET "DA<3>" LOC = "R6" ;
+NET "DA<2>" LOC = "P6" ;
+NET "DA<1>" LOC = "R1" ;
+NET "DA<0>" LOC = "R2" ;
+
+NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
+
+NET "PPS_IN" LOC = "M5" ;
+
+NET "io_tx<0>" LOC = "AB20" ;
+NET "io_tx<1>" LOC = "Y17" ;
+NET "io_tx<2>" LOC = "Y16" ;
+NET "io_tx<3>" LOC = "U16" ;
+NET "io_tx<4>" LOC = "V16" ;
+NET "io_tx<5>" LOC = "AB19" ;
+NET "io_tx<6>" LOC = "AA19" ;
+NET "io_tx<7>" LOC = "U14" ;
+NET "io_tx<8>" LOC = "U15" ;
+NET "io_tx<9>" LOC = "AB17" ;
+NET "io_tx<10>" LOC = "AB18" ;
+NET "io_tx<11>" LOC = "Y13" ;
+NET "io_tx<12>" LOC = "W14" ;
+NET "io_tx<13>" LOC = "U13" ;
+NET "io_tx<14>" LOC = "AA15" ;
+NET "io_tx<15>" LOC = "AB14" ;
+
+NET "io_rx<0>" LOC = "Y8" ;
+NET "io_rx<1>" LOC = "Y9" ;
+NET "io_rx<2>" LOC = "V7" ;
+NET "io_rx<3>" LOC = "U8" ;
+NET "io_rx<4>" LOC = "V10" ;
+NET "io_rx<5>" LOC = "U9" ;
+NET "io_rx<6>" LOC = "AB7" ;
+NET "io_rx<7>" LOC = "AA8" ;
+NET "io_rx<8>" LOC = "W8" ;
+NET "io_rx<9>" LOC = "V8" ;
+NET "io_rx<10>" LOC = "AB5" ;
+NET "io_rx<11>" LOC = "AB6" ;
+NET "io_rx<12>" LOC = "AB4" ;
+NET "io_rx<13>" LOC = "AA4" ;
+NET "io_rx<14>" LOC = "W5" ;
+NET "io_rx<15>" LOC = "Y4" ;
+
+#NET "CLKOUT2_CODEC" LOC = "U12" ;
+#NET "CLKOUT1_CODEC" LOC = "V12" ;
+
+## FPGA Config Pins
+#NET "fpga_cfg_prog_b" LOC = "A2" ;
+#NET "fpga_cfg_done" LOC = "AB21" ;
+#NET "fpga_cfg_din" LOC = "W17" ;
+#NET "fpga_cfg_cclk" LOC = "V17" ;
+#NET "fpga_cfg_init_b" LOC = "W15" ;
+
+## Unused
+#NET "unnamed_net53" LOC = "B1" ; # TMS
+#NET "unnamed_net52" LOC = "B22" ; # TDO
+#NET "unnamed_net51" LOC = "D2" ; # TDI
+#NET "unnamed_net50" LOC = "A21" ; # TCK
+#NET "unnamed_net59" LOC = "F7" ; # PUDC_B
+#NET "unnamed_net58" LOC = "V6" ; # M2
+#NET "unnamed_net57" LOC = "AA3" ; # M1
+#NET "unnamed_net56" LOC = "AB3" ; # M0
+#NET "GND" LOC = "V19" ; # Suspend, unused
diff --git a/fpga/usrp2/top/E1x0/E1x0.v b/fpga/usrp2/top/E1x0/E1x0.v
new file mode 100644
index 000000000..e7b0a4e00
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/E1x0.v
@@ -0,0 +1,196 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module E1x0
+ (input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+ output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+ input debug_pb, output FPGA_TXD, input FPGA_RXD,
+ output fpga_txd1, input fpga_rxd1, input overo_txd1, output overo_rxd1,
+
+ // GPMC
+ input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+ input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
+ input EM_NWE, input EM_NOE,
+
+ inout db_sda, inout db_scl, // I2C
+
+ output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI
+ output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI
+ output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI
+ output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI
+
+ input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
+ input overo_gpio65, input overo_gpio128, input overo_gpio145, output overo_gpio147, //aux SPI
+
+ output overo_gpio144, output overo_gpio146, // Fifo controls
+ input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO
+ input overo_gpio23, input overo_gpio64, input overo_gpio127, // Misc GPIO
+ input overo_gpio176, input overo_gpio163, input overo_gpio170, // Misc GPIO
+
+ inout [15:0] io_tx, inout [15:0] io_rx,
+
+ output [13:0] TX, output TXSYNC, output TXBLANK,
+ input [11:0] DA, input [11:0] DB, input RXSYNC,
+
+ input PPS_IN
+ );
+
+ assign FPGA_TXD = 0; //dont care
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Clocking
+ wire clk_fpga;
+ wire reset;
+
+ reg async_reset;
+ always @(negedge EM_CLK) begin
+ async_reset <= ~EM_NCS6 && ~EM_NWE && (EM_A[9:2] == 8'hff) && EM_D[0];
+ end
+
+ IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
+ clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+ reset_sync reset_sync(.clk(clk_fpga), .reset_in(async_reset), .reset_out(reset));
+
+ // /////////////////////////////////////////////////////////////////////////
+ // UART level conversion
+ assign fpga_txd1 = overo_txd1;
+ assign overo_rxd1 = fpga_rxd1;
+
+ // SPI
+ wire mosi, sclk, miso;
+ assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
+ assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0;
+ assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0;
+ //assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; //replaced by aux spi
+ assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) |
+ (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso);
+
+ //assign the aux spi to the cgen (bypasses control fifo)
+ assign cgen_sclk = overo_gpio65;
+ assign cgen_sen_b = overo_gpio128;
+ assign cgen_mosi = overo_gpio145;
+ wire has_resp; //re-purpose gpio for interrupt when we are not using aux spi
+ assign overo_gpio147 = (cgen_sen_b == 1'b0)? cgen_miso : has_resp;
+
+ wire _cgen_sen_b;
+ //assign cgen_sen_b = _cgen_sen_b; //replaced by aux spi
+
+ // /////////////////////////////////////////////////////////////////////////
+ // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
+
+ assign TXBLANK = 0;
+ wire [13:0] tx_i, tx_q;
+
+ reg[13:0] delay_q;
+ always @(posedge clk_fpga)
+ delay_q <= tx_q;
+
+ genvar i;
+ generate
+ for(i=0;i<14;i=i+1)
+ begin : gen_dacout
+ ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D0(tx_i[i]), // 1-bit data input (associated with C0)
+ .D1(delay_q[i]), // 1-bit data input (associated with C1)
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
+ end // block: gen_dacout
+ endgenerate
+ ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D0(1'b0), // 1-bit data input (associated with C0)
+ .D1(1'b1), // 1-bit data input (associated with C1)
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Main Core
+ wire [35:0] rx_data, tx_data, ctrl_data, resp_data;
+ wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy;
+ wire dsp_rx_run, dsp_tx_run;
+ wire [7:0] sen8;
+ assign {_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx} = sen8[3:0];
+ wire [31:0] core_debug;
+
+ assign debug_led = ~{PPS_IN, dsp_tx_run, dsp_rx_run, cgen_st_ld};
+ wire cgen_sync;
+ assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1};
+
+ u1plus_core #(
+ .NUM_RX_DSPS(2),
+ .DSP_RX_XTRA_FIFOSIZE(10),
+ .DSP_TX_XTRA_FIFOSIZE(10),
+ .USE_PACKET_PADDER(0)
+ ) core(
+ .clk(clk_fpga), .reset(reset),
+ .debug(core_debug), .debug_clk(debug_clk),
+
+ .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
+ .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
+ .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
+ .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
+
+ .dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run),
+ .clock_sync(cgen_sync),
+
+ .db_sda(db_sda), .db_scl(db_scl),
+ .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso),
+ .io_tx(io_tx), .io_rx(io_rx),
+ .tx_i(tx_i), .tx_q(tx_q),
+ .rx_i(DA), .rx_q(DB),
+ .pps_in(PPS_IN) );
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Interface between GPMC/host
+ wire [31:0] gpmc_debug;
+
+ gpmc #(.TXFIFOSIZE(13), .RXFIFOSIZE(13))
+ gpmc (.arst(async_reset),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
+ .EM_NOE(EM_NOE),
+
+ .rx_have_data(overo_gpio146), .tx_have_space(overo_gpio144),
+ .resp_have_data(has_resp),
+
+ .fifo_clk(clk_fpga), .fifo_rst(reset),
+ .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
+ .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
+ .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
+ .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
+
+ .debug(gpmc_debug));
+
+ //assign debug = gpmc_debug;
+ assign debug = core_debug;
+
+endmodule // E1x0
diff --git a/fpga/usrp2/top/E1x0/Makefile b/fpga/usrp2/top/E1x0/Makefile
new file mode 100644
index 000000000..0ca8ed2dd
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2011 Ettus Research LLC
+#
+
+all: E100 E110
+ find -name "*.twr" | xargs grep constraint | grep met
+
+clean:
+ rm -rf build*
+
+E100:
+ make -f Makefile.$@ bin
+
+E110:
+ make -f Makefile.$@ bin
+
+.PHONY: all clean
diff --git a/fpga/usrp2/top/E1x0/Makefile.E100 b/fpga/usrp2/top/E1x0/Makefile.E100
new file mode 100644
index 000000000..92334d987
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/Makefile.E100
@@ -0,0 +1,106 @@
+#
+# Copyright 2008-2012 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = E1x0
+BUILD_DIR = $(abspath build$(ISE)-E100)
+
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../gpmc/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+../B100/u1plus_core.v \
+E1x0.v \
+E1x0.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_DEFS)"
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110
new file mode 100644
index 000000000..e5be8d2fa
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/Makefile.E110
@@ -0,0 +1,106 @@
+#
+# Copyright 2008-2012 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = E1x0
+BUILD_DIR = $(abspath build$(ISE)-E110)
+
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../gpmc/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+../B100/u1plus_core.v \
+E1x0.v \
+E1x0.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_DEFS)"
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/E1x0/README b/fpga/usrp2/top/E1x0/README
new file mode 100644
index 000000000..14c7a4955
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/README
@@ -0,0 +1,4 @@
+
+make clean
+make sim
+./tb_u1e -lxt2
diff --git a/fpga/usrp2/top/E1x0/cmdfile b/fpga/usrp2/top/E1x0/cmdfile
new file mode 100644
index 000000000..291c723b8
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/cmdfile
@@ -0,0 +1,20 @@
+
+# My stuff
+-y .
+-y ../../control_lib
+-y ../../control_lib/newfifo
+-y ../../sdr_lib
+-y ../../timing
+-y ../../coregen
+-y ../../gpmc
+
+# Models
+-y ../../models
+-y /opt/Xilinx/10.1/ISE/verilog/src/unisims
+
+# Open Cores
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
+
diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile
new file mode 100755
index 000000000..dd88094ff
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/core_compile
@@ -0,0 +1,3 @@
+iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models
+
+
diff --git a/fpga/usrp2/top/E1x0/make.sim b/fpga/usrp2/top/E1x0/make.sim
new file mode 100644
index 000000000..1c163884c
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/make.sim
@@ -0,0 +1,7 @@
+all: sim
+
+sim:
+ iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e
+
+clean:
+ rm -f tb_u1e *.vcd *.lxt a.out
diff --git a/fpga/usrp2/top/E1x0/tb_u1e.v b/fpga/usrp2/top/E1x0/tb_u1e.v
new file mode 100644
index 000000000..188190f04
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/tb_u1e.v
@@ -0,0 +1,58 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+`timescale 1ps / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module tb_u1e();
+
+ wire [2:0] debug_led;
+ wire [31:0] debug;
+ wire [1:0] debug_clk;
+
+ xlnx_glbl glbl (.GSR(),.GTS());
+
+ initial begin
+ $dumpfile("tb_u1e.lxt");
+ $dumpvars(0,tb_u1e);
+ end
+
+ // GPMC
+ wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
+ wire [15:0] EM_D;
+ wire [10:1] EM_A;
+ wire [1:0] EM_NBE;
+
+ reg clk_fpga = 0, rst_fpga = 1;
+ always #15625 clk_fpga = ~clk_fpga;
+
+ initial #200000
+ @(posedge clk_fpga)
+ rst_fpga <= 0;
+
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga),
+ .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+ gpmc_model_async gpmc_model_async
+ (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+endmodule // tb_u1e
diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf
new file mode 100644
index 000000000..6bd559426
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/timing.ucf
@@ -0,0 +1,23 @@
+
+NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
+
+NET "EM_CLK" TNM_NET = "EM_CLK";
+TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 18867 ps HIGH 50 %;
+
+#constrain GPMC IO
+INST "EM_D<*>" TNM = gpmc_net_out;
+INST "EM_D<*>" TNM = gpmc_net;
+INST "EM_A<*>" TNM = gpmc_net;
+INST "EM_NCS4" TNM = gpmc_net;
+INST "EM_NCS6" TNM = gpmc_net;
+INST "EM_NWE" TNM = gpmc_net;
+INST "EM_NOE" TNM = gpmc_net;
+
+TIMEGRP "gpmc_net" OFFSET = IN 7 ns VALID 14 ns BEFORE "EM_CLK" FALLING;
+TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read
+
+#constrain interrupt lines
+NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space
+NET "overo_gpio146" MAXDELAY = 5.5 ns; #have data
+NET "overo_gpio147" MAXDELAY = 5.5 ns; #have msg/aux spi miso
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 22:32:16 +0000