1 files changed, 27 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf
new file mode 100644
index 000000000..47c250c2f
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/timing.ucf
@@ -0,0 +1,27 @@
+
+NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
+
+NET "EM_CLK" TNM_NET = "EM_CLK";
+TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 12048 ps HIGH 50 %;
+
+#constrain GPMC IO
+NET "EM_D<*>" MAXDELAY = 5.5 ns;
+NET "EM_A<*>" MAXDELAY = 5.5 ns;
+NET "EM_NBE<*>" MAXDELAY = 5.5 ns;
+NET "EM_NCS4" MAXDELAY = 5.5 ns;
+NET "EM_NCS6" MAXDELAY = 5.5 ns;
+NET "EM_NWE" MAXDELAY = 5.5 ns;
+NET "EM_NOE" MAXDELAY = 5.5 ns;
+
+#constrain interrupt lines
+NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space
+NET "overo_gpio146" MAXDELAY = 5.5 ns; #have data
+NET "overo_gpio147" MAXDELAY = 5.5 ns; #have msg/aux spi miso
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;