2 files changed, 5 insertions, 5 deletions
diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v
index dcda974b4..e333e82aa 100644
--- a/fpga/usrp2/top/B100/B100.v
+++ b/fpga/usrp2/top/B100/B100.v
@@ -143,13 +143,13 @@ module B100
    always @(posedge clk_fpga)
      if(rxsync_0)
        begin
-	  rx_i <= rx_b;
-	  rx_q <= rx_a;
+	  rx_i <= ~rx_b;
+	  rx_q <= ~rx_a;
        end
      else
        begin
-	  rx_i <= rx_a;
-	  rx_q <= rx_b;
+	  rx_i <= ~rx_a;
+	  rx_q <= ~rx_b;
        end
    
    // /////////////////////////////////////////////////////////////////////////
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index c1d6767d1..74151ce98 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -413,7 +413,7 @@ module u1plus_core
    // Readback mux 32 -- Slave #7
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd3}; //major, minor
+   localparam compat_num = {16'd9, 16'd4}; //major, minor
 
    wire [31:0] reg_test32;