2 files changed, 5 insertions, 5 deletions
diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v
index 59bed6066..d26d0a0d0 100644
--- a/fpga/usrp2/top/B100/B100.v
+++ b/fpga/usrp2/top/B100/B100.v
@@ -147,13 +147,13 @@ module B100
    always @(posedge clk_fpga)
      if(rxsync_0)
        begin
-	  rx_i <= rx_b;
-	  rx_q <= rx_a;
+	  rx_i <= ~rx_b;
+	  rx_q <= ~rx_a;
        end
      else
        begin
-	  rx_i <= rx_a;
-	  rx_q <= rx_b;
+	  rx_i <= ~rx_a;
+	  rx_q <= ~rx_b;
        end
 
    // /////////////////////////////////////////////////////////////////////////
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index ef0ce51f7..423282153 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -71,7 +71,7 @@ module u1plus_core
     localparam SR_GPIO         = 224;     // 5
 
     //compatibility number -> increment when the fpga has been sufficiently altered
-    localparam compat_num = {16'd11, 16'd0}; //major, minor
+    localparam compat_num = {16'd11, 16'd1}; //major, minor
 
     //assign run signals used for ATR logic
     wire [NUM_RX_DSPS-1:0] run_rx_n;