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-rw-r--r--fpga/usrp2/top/B100/timing.ucf19
1 files changed, 19 insertions, 0 deletions
diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf
new file mode 100644
index 000000000..c4404e1d0
--- /dev/null
+++ b/fpga/usrp2/top/B100/timing.ucf
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+NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
+TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
+
+NET "IFCLK" TNM_NET = "IFCLK";
+TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %;
+
+#constrain FX2 IO
+INST "GPIF_D<*>" TNM = gpif_net_in;
+INST "GPIF_CTL<*>" TNM = gpif_net_in;
+
+INST "GPIF_D<*>" TNM = gpif_net_out;
+INST "GPIF_ADR<*>" TNM = gpif_net_out;
+INST "GPIF_SLWR" TNM = gpif_net_out;
+INST "GPIF_SLOE" TNM = gpif_net_out;
+INST "GPIF_SLRD" TNM = gpif_net_out;
+INST "GPIF_PKTEND" TNM = gpif_net_out;
+
+TIMEGRP "gpif_net_in" OFFSET = IN 7 ns VALID 14 ns BEFORE "IFCLK" RISING;
+TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING;