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-rw-r--r--fpga/usrp2/top/B100/Makefile.B1002
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/B100/Makefile.B100 b/fpga/usrp2/top/B100/Makefile.B100
index 3cdbb62c0..48dc7dfd3 100644
--- a/fpga/usrp2/top/B100/Makefile.B100
+++ b/fpga/usrp2/top/B100/Makefile.B100
@@ -71,7 +71,7 @@ SYNTHESIZE_PROPERTIES = \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
"Use Synchronous Set" Auto \
-"Verilog Macros" "$(CUSTOM_MOD_DEFS)"
+"Verilog Macros" "$(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"