4 files changed, 191 insertions, 75 deletions

diff --git a/fpga/usrp2/timing/time_64bit.v b/fpga/usrp2/timing/time_64bit.v
index 51c006962..33eb2b25a 100644
--- a/fpga/usrp2/timing/time_64bit.v
+++ b/fpga/usrp2/timing/time_64bit.v
@@ -3,27 +3,41 @@
 module time_64bit
   #(parameter TICKS_PER_SEC = 32'd100000000,
     parameter BASE = 0)
-    (input clk, input rst,
-     input set_stb, input [7:0] set_addr, input [31:0] set_data,  
-     input pps,
-     output [63:0] vita_time, output pps_int
-     );
-
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,  
+    input pps,
+    output [63:0] vita_time, output pps_int,
+    input exp_time_in, output exp_time_out,
+    output [31:0] debug
+    );
+   
    localparam 	   NEXT_SECS = 0;   
    localparam 	   NEXT_TICKS = 1;
    localparam      PPS_POLSRC = 2;
    localparam      PPS_IMM = 3;
    localparam      TPS = 4;
+   localparam      MIMO_SYNC = 5;
    
    reg [31:0] 	   seconds, ticks;
    wire 	   end_of_second;
    assign 	   vita_time = {seconds,ticks};
+   wire [63:0] 	   vita_time_rcvd;
    
    wire [31:0] 	   next_ticks_preset, next_seconds_preset;
    wire [31:0] 	   ticks_per_sec_reg;
    wire 	   set_on_pps_trig;
    reg 		   set_on_next_pps;
    wire 	   pps_polarity, pps_source, set_imm;
+   reg [1:0] 	   pps_del;
+   reg 		   pps_reg_p, pps_reg_n, pps_reg;
+   wire 	   pps_edge;
+
+   reg [15:0] 	   sync_counter;
+   wire 	   sync_rcvd;
+   wire [31:0] 	   mimo_secs, mimo_ticks;
+   wire 	   mimo_sync_now;
+   wire 	   mimo_sync;
+   wire [7:0] 	   sync_delay;
    
    setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -45,10 +59,10 @@ module time_64bit
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(ticks_per_sec_reg),.changed());
 
-   reg [1:0] 	   pps_del;
-   reg 		   pps_reg_p, pps_reg_n, pps_reg;
-   wire 	   pps_edge;
-   
+   setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({mimo_sync,sync_delay}),.changed());
+
    always @(posedge clk)  pps_reg_p <= pps;   
    always @(negedge clk)  pps_reg_n <= pps;
    always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n;
@@ -82,6 +96,11 @@ module time_64bit
 	  seconds <= next_seconds_preset;
 	  ticks <= next_ticks_preset;
        end
+     else if(mimo_sync_now)
+       begin
+	  seconds <= mimo_secs;
+	  ticks <= mimo_ticks;
+       end
      else if(ticks_plus_one == ticks_per_sec_reg)
        begin
 	  seconds <= seconds + 1;
@@ -91,5 +110,36 @@ module time_64bit
        ticks <= ticks_plus_one;
 
    assign pps_int = pps_edge;
+
+   // MIMO Connector Time Sync
+   wire send_sync = (sync_counter == 59999); // X % 10 = 9
+
+   always @(posedge clk)
+     if(rst)
+       sync_counter <= 0;
+     else
+       if(send_sync)
+	 sync_counter <= 0;
+       else
+	 sync_counter <= sync_counter + 1;
+   
+   time_sender time_sender
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time),
+      .send_sync(send_sync),
+      .exp_time_out(exp_time_out) );
+
+   time_receiver time_receiver
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time_rcvd),
+      .sync_rcvd(sync_rcvd),
+      .exp_time_in(exp_time_in) );
+
+   assign mimo_secs = vita_time_rcvd[63:32];
+   assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay};
+   assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC);
+
+   assign debug = { { 24'b0} ,
+		    { 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} };
    
 endmodule // time_64bit
diff --git a/fpga/usrp2/timing/time_receiver.v b/fpga/usrp2/timing/time_receiver.v
index 8e7d3f1ea..fd8651d29 100644
--- a/fpga/usrp2/timing/time_receiver.v
+++ b/fpga/usrp2/timing/time_receiver.v
@@ -1,9 +1,9 @@
 
 module time_receiver
   (input clk, input rst,
-   output [31:0] master_time,
-   output sync_rcvd,
-   input exp_pps_in);
+   output reg [63:0] vita_time,
+   output reg sync_rcvd,
+   input exp_time_in);
 
    wire       code_err, disp_err, dispout, complete_word;
    reg 	      disp_reg;
@@ -13,7 +13,7 @@ module time_receiver
    reg [8:0]  dataout_reg;
  	      
    always @(posedge clk)
-     shiftreg <= {exp_pps_in, shiftreg[9:1]};
+     shiftreg <= {exp_time_in, shiftreg[9:1]};
 
    localparam COMMA_0 = 10'h283;
    localparam COMMA_1 = 10'h17c;
@@ -55,40 +55,76 @@ module time_receiver
    localparam STATE_T1 = 2;
    localparam STATE_T2 = 3;
    localparam STATE_T3 = 4;
+   localparam STATE_T4 = 5;
+   localparam STATE_T5 = 6;
+   localparam STATE_T6 = 7;
+   localparam STATE_T7 = 8;
+   localparam STATE_TAIL = 9;
    
    localparam HEAD = 9'h13c;   
-
-   reg [7:0]  clock_a, clock_b, clock_c;
-   reg [2:0]  state;
+   localparam TAIL = 9'h1F7;
+   
+   reg [3:0]  state;
    
    always @(posedge clk)
      if(rst)
        state <= STATE_IDLE;
      else if(complete_word)
-       case(state)
-	 STATE_IDLE :
-	   if(dataout_reg == HEAD)
-	     state <= STATE_T0;
-	 STATE_T0 :
-	   begin
-	      clock_a <= dataout_reg[7:0];
-	      state <= STATE_T1;
-	   end
-	 STATE_T1 :
-	   begin
-	      clock_b <= dataout_reg[7:0];
-	      state <= STATE_T2;
-	   end
-	 STATE_T2 :
-	   begin
-	      clock_c <= dataout_reg[7:0];
-	      state <= STATE_T3;
-	   end
-	 STATE_T3 :
-	   state <= STATE_IDLE;
-       endcase // case(state)
-
-   assign master_time =  {clock_a, clock_b, clock_c, dataout_reg[7:0]};
-   assign sync_rcvd = (complete_word & (state == STATE_T3));
-
+       if(code_err | disp_err)
+	 state <= STATE_IDLE;
+       else
+	 case(state)
+	   STATE_IDLE :
+	     if(dataout_reg == HEAD)
+	       state <= STATE_T0;
+	   STATE_T0 :
+	     begin
+		vita_time[63:56] <= dataout_reg[7:0];
+		state <= STATE_T1;
+	     end
+	   STATE_T1 :
+	     begin
+		vita_time[55:48] <= dataout_reg[7:0];
+		state <= STATE_T2;
+	     end
+	   STATE_T2 :
+	     begin
+		vita_time[47:40] <= dataout_reg[7:0];
+		state <= STATE_T3;
+	     end
+	   STATE_T3 :
+	     begin
+		vita_time[39:32] <= dataout_reg[7:0];
+		state <= STATE_T4;
+	     end
+	   STATE_T4 :
+	     begin
+		vita_time[31:24] <= dataout_reg[7:0];
+		state <= STATE_T5;
+	     end
+	   STATE_T5 :
+	     begin
+		vita_time[23:16] <= dataout_reg[7:0];
+		state <= STATE_T6;
+	     end
+	   STATE_T6 :
+	     begin
+		vita_time[15:8] <= dataout_reg[7:0];
+		state <= STATE_T7;
+	     end
+	   STATE_T7 :
+	     begin
+		vita_time[7:0] <= dataout_reg[7:0];
+		state <= STATE_TAIL;
+	     end
+	   STATE_TAIL :
+	     state <= STATE_IDLE;
+	 endcase // case(state)
+   
+   always @(posedge clk)
+     if(rst)
+       sync_rcvd <= 0;
+     else
+       sync_rcvd <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL));
+   
 endmodule // time_sender
diff --git a/fpga/usrp2/timing/time_sender.v b/fpga/usrp2/timing/time_sender.v
index aa2fcbbdb..f4ee5226a 100644
--- a/fpga/usrp2/timing/time_sender.v
+++ b/fpga/usrp2/timing/time_sender.v
@@ -2,23 +2,23 @@
 
 module time_sender
   (input clk, input rst,
-   input [31:0] master_time,
+   input [63:0] vita_time,
    input send_sync,
-   output exp_pps_out);
+   output reg exp_time_out);
 
    reg [7:0] datain;
    reg 	     k;
    wire [9:0] dataout;
-   reg [9:0] dataout_reg;
-   reg 	     disp_reg;
-   wire      disp, new_word;
+   reg [9:0]  dataout_reg;
+   reg 	      disp_reg;
+   wire       disp, new_word;
+   reg [4:0]  state;
+   reg [3:0]  bit_count;
    
    encode_8b10b encode_8b10b 
      (.datain({k,datain}),.dispin(disp_reg),
       .dataout(dataout),.dispout(disp));
 
-   assign    exp_pps_out = dataout_reg[0];
-
    always @(posedge clk)
      if(rst)
        disp_reg <= 0;
@@ -33,9 +33,9 @@ module time_sender
      else
        dataout_reg <= {1'b0,dataout_reg[9:1]};
    
-   reg [4:0] state;
-   reg [3:0] bit_count;
-
+   always @(posedge clk)
+     exp_time_out <= dataout_reg[0];
+   
    assign    new_word = (bit_count == 9);
    
    always @(posedge clk)
@@ -52,17 +52,23 @@ module time_sender
    localparam SEND_T1 = 3;
    localparam SEND_T2 = 4;
    localparam SEND_T3 = 5;
+   localparam SEND_T4 = 6;
+   localparam SEND_T5 = 7;
+   localparam SEND_T6 = 8;
+   localparam SEND_T7 = 9;
+   localparam SEND_TAIL = 10;
 
    localparam COMMA = 8'hBC;
    localparam HEAD = 8'h3C;
-
-   reg [31:0] master_time_reg;
+   localparam TAIL = 8'hF7;
+   
+   reg [63:0] vita_time_reg;
    
    always @(posedge clk)
      if(rst)
-       master_time_reg <= 0;
+       vita_time_reg <= 0;
      else if(send_sync)
-       master_time_reg <= master_time;
+       vita_time_reg <= vita_time;
    
    always @(posedge clk)
      if(rst)
@@ -84,27 +90,51 @@ module time_sender
 	     end
 	   SEND_T0 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[31:24] };
+		{k,datain} <= {1'b0, vita_time_reg[63:56] };
 		state <= SEND_T1;
 	     end
 	   SEND_T1 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[23:16]};
+		{k,datain} <= {1'b0, vita_time_reg[55:48]};
 		state <= SEND_T2;
 	     end
 	   SEND_T2 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[15:8]};
+		{k,datain} <= {1'b0, vita_time_reg[47:40]};
 		state <= SEND_T3;
 	     end
 	   SEND_T3 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[7:0]};
+		{k,datain} <= {1'b0, vita_time_reg[39:32]};
+		state <= SEND_T4;
+	     end
+	   SEND_T4 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[31:24]};
+		state <= SEND_T5;
+	     end
+	   SEND_T5 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[23:16]};
+		state <= SEND_T6;
+	     end
+	   SEND_T6 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[15:8]};
+		state <= SEND_T7;
+	     end
+	   SEND_T7 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[7:0]};
+		state <= SEND_TAIL;
+	     end
+	   SEND_TAIL :
+	     begin
+		{k,datain} <= {1'b1, TAIL};
 		state <= SEND_IDLE;
 	     end
 	   default :
 	     state <= SEND_IDLE;
 	 endcase // case(state)
    
-   
 endmodule // time_sender
diff --git a/fpga/usrp2/timing/time_transfer_tb.v b/fpga/usrp2/timing/time_transfer_tb.v
index 2b75c60bd..0c164f82c 100644
--- a/fpga/usrp2/timing/time_transfer_tb.v
+++ b/fpga/usrp2/timing/time_transfer_tb.v
@@ -18,12 +18,12 @@ module time_transfer_tb();
    
    initial #100000000 $finish;
 
-   wire exp_pps, pps, pps_rcv;
-   wire [31:0] master_clock_rcv;
-   reg [31:0]  master_clock = 0;
-   reg [31:0]  counter = 0;
+   wire exp_time, pps, pps_rcv;
+   wire [63:0] vita_time_rcv;
+   reg [63:0]  vita_time = 0;
+   reg [63:0]  counter = 0;
 
-   localparam  PPS_PERIOD = 109;
+   localparam  PPS_PERIOD = 439; // PPS_PERIOD % 10 must = 9
    always @(posedge clk)
      if(counter == PPS_PERIOD)
        counter <= 0;
@@ -32,19 +32,19 @@ module time_transfer_tb();
    assign      pps = (counter == (PPS_PERIOD-1));
    
    always @(posedge clk)
-     master_clock <= master_clock + 1;
+     vita_time <= vita_time + 1;
    
    time_sender time_sender
      (.clk(clk),.rst(rst),
-      .master_clock(master_clock),
-      .pps(pps),
-      .exp_pps_out(exp_pps) );
+      .vita_time(vita_time),
+      .send_sync(pps),
+      .exp_time_out(exp_time) );
 
    time_receiver time_receiver
      (.clk(clk),.rst(rst),
-      .master_clock(master_clock_rcv),
-      .pps(pps_rcv),
-      .exp_pps_in(exp_pps) );
+      .vita_time(vita_time_rcv),
+      .sync_rcvd(pps_rcv),
+      .exp_time_in(exp_time) );
 
-   wire [31:0] delta = master_clock - master_clock_rcv;
+   wire [31:0] delta = vita_time - vita_time_rcv;
 endmodule // time_transfer_tb