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-rw-r--r--fpga/usrp2/timing/time_64bit.v48
-rw-r--r--fpga/usrp2/timing/time_compare.v44
2 files changed, 23 insertions, 69 deletions
diff --git a/fpga/usrp2/timing/time_64bit.v b/fpga/usrp2/timing/time_64bit.v
index 03df07108..6f335890e 100644
--- a/fpga/usrp2/timing/time_64bit.v
+++ b/fpga/usrp2/timing/time_64bit.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
module time_64bit
- #(parameter TICKS_PER_SEC = 32'd100000000,
+ #(
parameter BASE = 0)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -31,23 +31,20 @@ module time_64bit
output [31:0] debug
);
- localparam NEXT_SECS = 0;
- localparam NEXT_TICKS = 1;
+ localparam NEXT_TICKS_HI = 0;
+ localparam NEXT_TICKS_LO = 1;
localparam PPS_POLSRC = 2;
localparam PPS_IMM = 3;
- localparam TPS = 4;
localparam MIMO_SYNC = 5;
- reg [31:0] seconds, ticks;
- wire end_of_second;
+ reg [63:0] ticks;
always @(posedge clk)
- vita_time <= {seconds,ticks};
+ vita_time <= ticks;
wire [63:0] vita_time_rcvd;
- wire [31:0] next_ticks_preset, next_seconds_preset;
- wire [31:0] ticks_per_sec_reg;
+ wire [63:0] next_ticks_preset;
wire set_on_pps_trig;
reg set_on_next_pps;
wire pps_polarity, pps_source, set_imm;
@@ -57,18 +54,18 @@ module time_64bit
reg [15:0] sync_counter;
wire sync_rcvd;
- wire [31:0] mimo_secs, mimo_ticks;
+ wire [63:0] mimo_ticks;
wire mimo_sync_now;
wire mimo_sync;
wire [7:0] sync_delay;
- setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
+ setting_reg #(.my_addr(BASE+NEXT_TICKS_LO)) sr_next_ticks_lo
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(next_ticks_preset),.changed());
+ .in(set_data),.out(next_ticks_preset[31:0]),.changed());
- setting_reg #(.my_addr(BASE+NEXT_SECS)) sr_next_secs
+ setting_reg #(.my_addr(BASE+NEXT_TICKS_HI)) sr_next_ticks_hi
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
+ .in(set_data),.out(next_ticks_preset[63:32]),.changed(set_on_pps_trig));
setting_reg #(.my_addr(BASE+PPS_POLSRC), .width(2)) sr_pps_polsrc
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -78,10 +75,6 @@ module time_64bit
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(set_imm),.changed());
- setting_reg #(.my_addr(BASE+TPS), .at_reset(TICKS_PER_SEC)) sr_tps
- (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(ticks_per_sec_reg),.changed());
-
setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({mimo_sync,sync_delay}),.changed());
@@ -110,29 +103,21 @@ module time_64bit
else if(set_imm | pps_edge)
set_on_next_pps <= 0;
- wire [31:0] ticks_plus_one = ticks + 1;
+ wire [63:0] ticks_plus_one = ticks + 1;
always @(posedge clk)
if(rst)
begin
- seconds <= 32'd0;
- ticks <= 32'd0;
+ ticks <= 64'd0;
end
else if((set_imm | pps_edge) & set_on_next_pps)
begin
- seconds <= next_seconds_preset;
ticks <= next_ticks_preset;
end
else if(mimo_sync_now)
begin
- seconds <= mimo_secs;
ticks <= mimo_ticks;
end
- else if(ticks_plus_one == ticks_per_sec_reg)
- begin
- seconds <= seconds + 1;
- ticks <= 0;
- end
else
ticks <= ticks_plus_one;
@@ -162,9 +147,8 @@ module time_64bit
.sync_rcvd(sync_rcvd),
.exp_time_in(exp_time_in) );
- assign mimo_secs = vita_time_rcvd[63:32];
- assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay};
- assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC);
+ assign mimo_ticks = vita_time_rcvd[63:0] + {48'd0,sync_delay};
+ assign mimo_sync_now = mimo_sync & sync_rcvd;
assign debug = { { 24'b0} ,
{ 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} };
diff --git a/fpga/usrp2/timing/time_compare.v b/fpga/usrp2/timing/time_compare.v
index 54ea000d6..21607f51c 100644
--- a/fpga/usrp2/timing/time_compare.v
+++ b/fpga/usrp2/timing/time_compare.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -16,49 +16,19 @@
//
-// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second
+// 64 bits worth of ticks
module time_compare
(input [63:0] time_now,
input [63:0] trigger_time,
output now,
output early,
- output late,
+ output late,
output too_early);
-
- wire sec_match = (time_now[63:32] == trigger_time[63:32]);
- wire sec_late = (time_now[63:32] > trigger_time[63:32]);
- wire tick_match = (time_now[31:0] == trigger_time[31:0]);
- wire tick_late = (time_now[31:0] > trigger_time[31:0]);
-/*
- assign now = sec_match & tick_match;
- assign late = sec_late | (sec_match & tick_late);
- assign early = ~now & ~late;
-*/
+ assign now = time_now == trigger_time;
+ assign late = time_now > trigger_time;
+ assign early = ~now & ~late;
+ assign too_early = 0; //not implemented
- /*
- assign now = (time_now == trigger_time);
- assign late = (time_now > trigger_time);
- assign early = (time_now < trigger_time);
- */
-
- // Compare fewer bits instead of 64 to speed up logic
- // Unused bits are not significant
- // Top bit of seconds would put us in year 2038, long after
- // the warranty has run out :)
- // Top 5 bits of ticks are always zero for clocks less than 134MHz
- // "late" can drop bottom few bits of ticks, and just delay signaling
- // of late.
- // "now" cannot drop those bits, it needs to be exact.
-
- wire [57:0] short_now = {time_now[62:32],time_now[26:0]};
- wire [57:0] short_trig = {trigger_time[62:32],trigger_time[26:0]};
-
- assign now = (short_now == short_trig);
- assign late = (short_now[57:5] > short_trig[57:5]);
- assign early = (short_now < short_trig);
-
- assign too_early = (trigger_time[63:32] > (time_now[63:32] + 4)); // Don't wait too long
-
endmodule // time_compare
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