1 files changed, 69 insertions, 33 deletions

diff --git a/fpga/usrp2/timing/time_receiver.v b/fpga/usrp2/timing/time_receiver.v
index 8e7d3f1ea..fd8651d29 100644
--- a/fpga/usrp2/timing/time_receiver.v
+++ b/fpga/usrp2/timing/time_receiver.v
@@ -1,9 +1,9 @@
 
 module time_receiver
   (input clk, input rst,
-   output [31:0] master_time,
-   output sync_rcvd,
-   input exp_pps_in);
+   output reg [63:0] vita_time,
+   output reg sync_rcvd,
+   input exp_time_in);
 
    wire       code_err, disp_err, dispout, complete_word;
    reg 	      disp_reg;
@@ -13,7 +13,7 @@ module time_receiver
    reg [8:0]  dataout_reg;
  	      
    always @(posedge clk)
-     shiftreg <= {exp_pps_in, shiftreg[9:1]};
+     shiftreg <= {exp_time_in, shiftreg[9:1]};
 
    localparam COMMA_0 = 10'h283;
    localparam COMMA_1 = 10'h17c;
@@ -55,40 +55,76 @@ module time_receiver
    localparam STATE_T1 = 2;
    localparam STATE_T2 = 3;
    localparam STATE_T3 = 4;
+   localparam STATE_T4 = 5;
+   localparam STATE_T5 = 6;
+   localparam STATE_T6 = 7;
+   localparam STATE_T7 = 8;
+   localparam STATE_TAIL = 9;
    
    localparam HEAD = 9'h13c;   
-
-   reg [7:0]  clock_a, clock_b, clock_c;
-   reg [2:0]  state;
+   localparam TAIL = 9'h1F7;
+   
+   reg [3:0]  state;
    
    always @(posedge clk)
      if(rst)
        state <= STATE_IDLE;
      else if(complete_word)
-       case(state)
-	 STATE_IDLE :
-	   if(dataout_reg == HEAD)
-	     state <= STATE_T0;
-	 STATE_T0 :
-	   begin
-	      clock_a <= dataout_reg[7:0];
-	      state <= STATE_T1;
-	   end
-	 STATE_T1 :
-	   begin
-	      clock_b <= dataout_reg[7:0];
-	      state <= STATE_T2;
-	   end
-	 STATE_T2 :
-	   begin
-	      clock_c <= dataout_reg[7:0];
-	      state <= STATE_T3;
-	   end
-	 STATE_T3 :
-	   state <= STATE_IDLE;
-       endcase // case(state)
-
-   assign master_time =  {clock_a, clock_b, clock_c, dataout_reg[7:0]};
-   assign sync_rcvd = (complete_word & (state == STATE_T3));
-
+       if(code_err | disp_err)
+	 state <= STATE_IDLE;
+       else
+	 case(state)
+	   STATE_IDLE :
+	     if(dataout_reg == HEAD)
+	       state <= STATE_T0;
+	   STATE_T0 :
+	     begin
+		vita_time[63:56] <= dataout_reg[7:0];
+		state <= STATE_T1;
+	     end
+	   STATE_T1 :
+	     begin
+		vita_time[55:48] <= dataout_reg[7:0];
+		state <= STATE_T2;
+	     end
+	   STATE_T2 :
+	     begin
+		vita_time[47:40] <= dataout_reg[7:0];
+		state <= STATE_T3;
+	     end
+	   STATE_T3 :
+	     begin
+		vita_time[39:32] <= dataout_reg[7:0];
+		state <= STATE_T4;
+	     end
+	   STATE_T4 :
+	     begin
+		vita_time[31:24] <= dataout_reg[7:0];
+		state <= STATE_T5;
+	     end
+	   STATE_T5 :
+	     begin
+		vita_time[23:16] <= dataout_reg[7:0];
+		state <= STATE_T6;
+	     end
+	   STATE_T6 :
+	     begin
+		vita_time[15:8] <= dataout_reg[7:0];
+		state <= STATE_T7;
+	     end
+	   STATE_T7 :
+	     begin
+		vita_time[7:0] <= dataout_reg[7:0];
+		state <= STATE_TAIL;
+	     end
+	   STATE_TAIL :
+	     state <= STATE_IDLE;
+	 endcase // case(state)
+   
+   always @(posedge clk)
+     if(rst)
+       sync_rcvd <= 0;
+     else
+       sync_rcvd <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL));
+   
 endmodule // time_sender