1 files changed, 60 insertions, 10 deletions

diff --git a/fpga/usrp2/timing/time_64bit.v b/fpga/usrp2/timing/time_64bit.v
index 51c006962..33eb2b25a 100644
--- a/fpga/usrp2/timing/time_64bit.v
+++ b/fpga/usrp2/timing/time_64bit.v
@@ -3,27 +3,41 @@
 module time_64bit
   #(parameter TICKS_PER_SEC = 32'd100000000,
     parameter BASE = 0)
-    (input clk, input rst,
-     input set_stb, input [7:0] set_addr, input [31:0] set_data,  
-     input pps,
-     output [63:0] vita_time, output pps_int
-     );
-
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,  
+    input pps,
+    output [63:0] vita_time, output pps_int,
+    input exp_time_in, output exp_time_out,
+    output [31:0] debug
+    );
+   
    localparam 	   NEXT_SECS = 0;   
    localparam 	   NEXT_TICKS = 1;
    localparam      PPS_POLSRC = 2;
    localparam      PPS_IMM = 3;
    localparam      TPS = 4;
+   localparam      MIMO_SYNC = 5;
    
    reg [31:0] 	   seconds, ticks;
    wire 	   end_of_second;
    assign 	   vita_time = {seconds,ticks};
+   wire [63:0] 	   vita_time_rcvd;
    
    wire [31:0] 	   next_ticks_preset, next_seconds_preset;
    wire [31:0] 	   ticks_per_sec_reg;
    wire 	   set_on_pps_trig;
    reg 		   set_on_next_pps;
    wire 	   pps_polarity, pps_source, set_imm;
+   reg [1:0] 	   pps_del;
+   reg 		   pps_reg_p, pps_reg_n, pps_reg;
+   wire 	   pps_edge;
+
+   reg [15:0] 	   sync_counter;
+   wire 	   sync_rcvd;
+   wire [31:0] 	   mimo_secs, mimo_ticks;
+   wire 	   mimo_sync_now;
+   wire 	   mimo_sync;
+   wire [7:0] 	   sync_delay;
    
    setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -45,10 +59,10 @@ module time_64bit
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(ticks_per_sec_reg),.changed());
 
-   reg [1:0] 	   pps_del;
-   reg 		   pps_reg_p, pps_reg_n, pps_reg;
-   wire 	   pps_edge;
-   
+   setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({mimo_sync,sync_delay}),.changed());
+
    always @(posedge clk)  pps_reg_p <= pps;   
    always @(negedge clk)  pps_reg_n <= pps;
    always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n;
@@ -82,6 +96,11 @@ module time_64bit
 	  seconds <= next_seconds_preset;
 	  ticks <= next_ticks_preset;
        end
+     else if(mimo_sync_now)
+       begin
+	  seconds <= mimo_secs;
+	  ticks <= mimo_ticks;
+       end
      else if(ticks_plus_one == ticks_per_sec_reg)
        begin
 	  seconds <= seconds + 1;
@@ -91,5 +110,36 @@ module time_64bit
        ticks <= ticks_plus_one;
 
    assign pps_int = pps_edge;
+
+   // MIMO Connector Time Sync
+   wire send_sync = (sync_counter == 59999); // X % 10 = 9
+
+   always @(posedge clk)
+     if(rst)
+       sync_counter <= 0;
+     else
+       if(send_sync)
+	 sync_counter <= 0;
+       else
+	 sync_counter <= sync_counter + 1;
+   
+   time_sender time_sender
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time),
+      .send_sync(send_sync),
+      .exp_time_out(exp_time_out) );
+
+   time_receiver time_receiver
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time_rcvd),
+      .sync_rcvd(sync_rcvd),
+      .exp_time_in(exp_time_in) );
+
+   assign mimo_secs = vita_time_rcvd[63:32];
+   assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay};
+   assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC);
+
+   assign debug = { { 24'b0} ,
+		    { 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} };
    
 endmodule // time_64bit