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-rw-r--r--fpga/usrp2/simple_gemac/Makefile.srcs2
-rw-r--r--fpga/usrp2/simple_gemac/ethrx_realign.v72
-rw-r--r--fpga/usrp2/simple_gemac/ethtx_realign.v77
-rw-r--r--fpga/usrp2/simple_gemac/simple_gemac_wrapper.v13
-rw-r--r--fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v1
5 files changed, 160 insertions, 5 deletions
diff --git a/fpga/usrp2/simple_gemac/Makefile.srcs b/fpga/usrp2/simple_gemac/Makefile.srcs
index b82e64208..7bcc58c91 100644
--- a/fpga/usrp2/simple_gemac/Makefile.srcs
+++ b/fpga/usrp2/simple_gemac/Makefile.srcs
@@ -24,4 +24,6 @@ miim/eth_miim.v \
miim/eth_clockgen.v \
miim/eth_outputcontrol.v \
miim/eth_shiftreg.v \
+ethtx_realign.v \
+ethrx_realign.v \
))
diff --git a/fpga/usrp2/simple_gemac/ethrx_realign.v b/fpga/usrp2/simple_gemac/ethrx_realign.v
new file mode 100644
index 000000000..0a369c914
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/ethrx_realign.v
@@ -0,0 +1,72 @@
+
+// NOTE: Will not work with single-line frames
+
+module ethrx_realign
+ (input clk, input reset, input clear,
+ input [35:0] datain, input src_rdy_i, output dst_rdy_o,
+ output [35:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+ reg [1:0] state;
+ reg [15:0] held;
+ reg [1:0] held_occ;
+
+ wire xfer_in = src_rdy_i & dst_rdy_o;
+ wire xfer_out = src_rdy_o & dst_rdy_i;
+
+ wire sof_in = datain[32];
+ wire eof_in = datain[33];
+ wire [1:0] occ_in = datain[35:34];
+ wire sof_out, eof_out;
+ wire [1:0] occ_out;
+
+ always @(posedge clk)
+ if(reset | clear)
+ begin
+ held <= 0;
+ held_occ <= 0;
+ end
+ else if(xfer_in)
+ begin
+ held <= datain[15:0];
+ held_occ <= datain[35:34];
+ end
+
+ localparam RE_IDLE = 0;
+ localparam RE_HELD = 1;
+ localparam RE_DONE = 2;
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= RE_IDLE;
+ else
+ case(state)
+ RE_IDLE :
+ if(src_rdy_i & dst_rdy_i)
+ if(eof_in)
+ state <= RE_DONE;
+ else
+ state <= RE_HELD;
+
+ RE_HELD :
+ if(src_rdy_i & dst_rdy_i & eof_in)
+ if((occ_in==0)|(occ_in==3))
+ state <= RE_DONE;
+ else
+ state <= RE_IDLE;
+
+ RE_DONE :
+ if(dst_rdy_i)
+ state <= RE_IDLE;
+
+ endcase // case (state)
+
+
+ assign sof_out = (state == RE_IDLE);
+ assign eof_out = (state == RE_DONE) | (occ_in == 1) | (occ_in == 2);
+ assign occ_out = (state == RE_DONE) ? ((held_occ == 3) ? 1 : 2) :
+ (occ_in == 1) ? 3 : 0;
+
+ assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]};
+ assign src_rdy_o = (state == RE_DONE) | src_rdy_i;
+ assign dst_rdy_o = dst_rdy_i & ((state == RE_IDLE)|(state == RE_HELD));
+endmodule // ethrx_realign
diff --git a/fpga/usrp2/simple_gemac/ethtx_realign.v b/fpga/usrp2/simple_gemac/ethtx_realign.v
new file mode 100644
index 000000000..be53abf4c
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/ethtx_realign.v
@@ -0,0 +1,77 @@
+
+////////////////////////////////////////////////////////////////////////
+// Ethernet TX - Realign
+//
+// - removes a 2-byte pad from the front a fifo36 stream
+// - occupancy is preserved
+//
+
+module ethtx_realign
+ (input clk, input reset, input clear,
+ input [35:0] datain, input src_rdy_i, output dst_rdy_o,
+ output [35:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+ reg [1:0] state;
+ reg [15:0] held;
+ reg [1:0] held_occ;
+ reg held_sof;
+
+ wire xfer_in = src_rdy_i & dst_rdy_o;
+ wire xfer_out = src_rdy_o & dst_rdy_i;
+
+ wire sof_in = datain[32];
+ wire eof_in = datain[33];
+ wire [1:0] occ_in = datain[35:34];
+ wire occ_low = occ_in[1] ^ occ_in[0]; //occ is 1 or 2
+
+ always @(posedge clk)
+ if(reset | clear)
+ begin
+ held <= 0;
+ held_occ <= 0;
+ held_sof <= 0;
+ end
+ else if(xfer_in)
+ begin
+ held <= datain[15:0];
+ held_occ <= occ_in;
+ held_sof <= sof_in;
+ end
+
+ localparam RE_IDLE = 0;
+ localparam RE_HELD = 1;
+ localparam RE_DONE = 2;
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= RE_IDLE;
+ else
+ case(state)
+ RE_IDLE :
+ if(xfer_in & eof_in)
+ state <= RE_DONE;
+ else if(xfer_in & sof_in)
+ state <= RE_HELD;
+
+ RE_HELD :
+ if(xfer_in & xfer_out & eof_in)
+ if(occ_low)
+ state <= RE_IDLE;
+ else
+ state <= RE_DONE;
+
+ RE_DONE :
+ if(xfer_out)
+ state <= RE_IDLE;
+
+ endcase // case (state)
+
+ wire sof_out = held_sof;
+ wire eof_out = (state == RE_HELD)? (eof_in & occ_low) : (state == RE_DONE);
+ wire [1:0] occ_out = ((state == RE_DONE)? held_occ : occ_in) ^ 2'b10; //(occ + 2)%4
+
+ assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]};
+ assign src_rdy_o = (state == RE_HELD)? src_rdy_i : (state == RE_DONE);
+ assign dst_rdy_o = (state == RE_HELD)? dst_rdy_i : (state == RE_IDLE);
+
+endmodule // ethtx_realign
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
index b783729d5..8390eb2c6 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
@@ -106,17 +106,22 @@ module simple_gemac_wrapper
// TX FIFO Chain
wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
wire [7:0] tx_ll_data;
- wire [35:0] tx_f36_data_int1;
- wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
+ wire [35:0] tx_f36_data_int1, tx_f36_data_int2;
+ wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_src_rdy_int2, tx_f36_dst_rdy_int2;
fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
(.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
.rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(),
.arst(reset));
-
+
+ ethtx_realign ethtx_realign
+ (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+ .datain(tx_f36_data_int1), .src_rdy_i(tx_f36_src_rdy_int1), .dst_rdy_o(tx_f36_dst_rdy_int1),
+ .dataout(tx_f36_data_int2), .src_rdy_o(tx_f36_src_rdy_int2), .dst_rdy_i(tx_f36_dst_rdy_int2) );
+
fifo36_to_ll8 fifo36_to_ll8
(.clk(tx_clk), .reset(tx_reset), .clear(clear),
- .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
+ .f36_data(tx_f36_data_int2), .f36_src_rdy_i(tx_f36_src_rdy_int2), .f36_dst_rdy_o(tx_f36_dst_rdy_int2),
.ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
.ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy));
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
index c155b7d41..2ac8b9be1 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
@@ -90,7 +90,6 @@ module simple_gemac_wrapper19
.datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1),
.dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) );
- //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
(.wclk(rx_clk), .datain(rx_f19_data_int2),
.src_rdy_i(rx_f19_src_rdy_int2), .dst_rdy_o(rx_f19_dst_rdy_int2), .space(rx_fifo_space),
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 09:21:34 +0000