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-rw-r--r--fpga/usrp2/simple_gemac/Makefile.srcs1
-rw-r--r--fpga/usrp2/simple_gemac/address_filter_promisc.v32
-rw-r--r--fpga/usrp2/simple_gemac/eth_tasks_f36.v6
-rw-r--r--fpga/usrp2/simple_gemac/simple_gemac_rx.v10
-rw-r--r--fpga/usrp2/simple_gemac/simple_gemac_wb.v27
-rwxr-xr-xfpga/usrp2/simple_gemac/simple_gemac_wrapper.build2
-rwxr-xr-xfpga/usrp2/simple_gemac/simple_gemac_wrapper19.build2
-rw-r--r--fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v10
-rw-r--r--fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v6
9 files changed, 64 insertions, 32 deletions
diff --git a/fpga/usrp2/simple_gemac/Makefile.srcs b/fpga/usrp2/simple_gemac/Makefile.srcs
index 6480cd5a4..b82e64208 100644
--- a/fpga/usrp2/simple_gemac/Makefile.srcs
+++ b/fpga/usrp2/simple_gemac/Makefile.srcs
@@ -17,6 +17,7 @@ delay_line.v \
flow_ctrl_tx.v \
flow_ctrl_rx.v \
address_filter.v \
+address_filter_promisc.v \
ll8_to_txmac.v \
rxmac_to_ll8.v \
miim/eth_miim.v \
diff --git a/fpga/usrp2/simple_gemac/address_filter_promisc.v b/fpga/usrp2/simple_gemac/address_filter_promisc.v
new file mode 100644
index 000000000..6047e7c93
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/address_filter_promisc.v
@@ -0,0 +1,32 @@
+
+
+module address_filter_promisc
+ (input clk,
+ input reset,
+ input go,
+ input [7:0] data,
+ output match,
+ output done);
+
+ reg [2:0] af_state;
+
+ always @(posedge clk)
+ if(reset)
+ af_state <= 0;
+ else
+ if(go)
+ af_state <= (data[0] == 1'b0) ? 1 : 7;
+ else
+ case(af_state)
+ 1 : af_state <= 2;
+ 2 : af_state <= 3;
+ 3 : af_state <= 4;
+ 4 : af_state <= 5;
+ 5 : af_state <= 6;
+ 6, 7 : af_state <= 0;
+ endcase // case (af_state)
+
+ assign match = (af_state==6);
+ assign done = (af_state==6)|(af_state==7);
+
+endmodule // address_filter_promisc
diff --git a/fpga/usrp2/simple_gemac/eth_tasks_f36.v b/fpga/usrp2/simple_gemac/eth_tasks_f36.v
index efd72778b..dc64971d4 100644
--- a/fpga/usrp2/simple_gemac/eth_tasks_f36.v
+++ b/fpga/usrp2/simple_gemac/eth_tasks_f36.v
@@ -4,11 +4,11 @@ task SendFlowCtrl;
input [15:0] fc_len;
begin
$display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
- pause_time <= fc_len;
+ //pause_time <= fc_len;
@(posedge eth_clk);
- pause_req <= 1;
+ //pause_req <= 1;
@(posedge eth_clk);
- pause_req <= 0;
+ //pause_req <= 0;
$display("Sent Flow Control");
end
endtask // SendFlowCtrl
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_rx.v b/fpga/usrp2/simple_gemac/simple_gemac_rx.v
index b02bb0758..32f517bb3 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_rx.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_rx.v
@@ -56,10 +56,10 @@ module simple_gemac_rx
else
rx_ack <= (rx_state == RX_GOODFRAME);
- wire is_ucast, is_bcast, is_mcast, is_pause;
- wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) |
- (pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all;
-
+ wire is_ucast, is_bcast, is_mcast, is_pause, is_any_ucast;
+ wire keep_packet = (pass_all & is_any_ucast) | (pass_ucast & is_ucast) | (pass_mcast & is_mcast) |
+ (pass_bcast & is_bcast) | (pass_pause & is_pause);
+
assign rx_data = rxd_del;
assign rx_error = (rx_state == RX_ERROR);
@@ -79,6 +79,8 @@ module simple_gemac_rx
.address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done());
address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
.address(48'h0180_c200_0001), .match(is_pause), .done());
+ address_filter_promisc af_promisc (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+ .match(is_any_ucast), .done());
always @(posedge rx_clk)
go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wb.v b/fpga/usrp2/simple_gemac/simple_gemac_wb.v
index 6df277e3e..1ef38be11 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wb.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wb.v
@@ -1,16 +1,17 @@
module wb_reg
#(parameter ADDR=0,
- parameter DEFAULT=0)
+ parameter DEFAULT=0,
+ parameter WIDTH=32)
(input clk, input rst,
input [5:0] adr, input wr_acc,
- input [31:0] dat_i, output reg [31:0] dat_o);
+ input [31:0] dat_i, output reg [WIDTH-1:0] dat_o);
always @(posedge clk)
if(rst)
dat_o <= DEFAULT;
else if(wr_acc & (adr == ADDR))
- dat_o <= dat_i;
+ dat_o <= dat_i[WIDTH-1:0];
endmodule // wb_reg
@@ -41,19 +42,19 @@ module simple_gemac_wb
wire [6:0] misc_settings;
assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings;
- wb_reg #(.ADDR(0),.DEFAULT(7'b0111001))
+ wb_reg #(.ADDR(0),.DEFAULT(7'b0111011),.WIDTH(7))
wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(misc_settings) );
- wb_reg #(.ADDR(1),.DEFAULT(0))
+ wb_reg #(.ADDR(1),.DEFAULT(0),.WIDTH(16))
wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) );
- wb_reg #(.ADDR(2),.DEFAULT(0))
+ wb_reg #(.ADDR(2),.DEFAULT(0),.WIDTH(32))
wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) );
- wb_reg #(.ADDR(3),.DEFAULT(0))
+ wb_reg #(.ADDR(3),.DEFAULT(0),.WIDTH(16))
wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) );
- wb_reg #(.ADDR(4),.DEFAULT(0))
+ wb_reg #(.ADDR(4),.DEFAULT(0),.WIDTH(32))
wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) );
@@ -80,15 +81,15 @@ module simple_gemac_wb
reg [15:0] MIIRX_DATA;
wire [2:0] MIISTATUS;
- wb_reg #(.ADDR(5),.DEFAULT(0))
+ wb_reg #(.ADDR(5),.DEFAULT(0),.WIDTH(9))
wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o({NoPre,Divider}) );
- wb_reg #(.ADDR(6),.DEFAULT(0))
+ wb_reg #(.ADDR(6),.DEFAULT(0),.WIDTH(13))
wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(MIIADDRESS) );
- wb_reg #(.ADDR(7),.DEFAULT(0))
+ wb_reg #(.ADDR(7),.DEFAULT(0),.WIDTH(16))
wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(CtrlData) );
@@ -133,11 +134,11 @@ module simple_gemac_wb
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart),
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) );
- wb_reg #(.ADDR(11),.DEFAULT(0))
+ wb_reg #(.ADDR(11),.DEFAULT(0),.WIDTH(16))
wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(pause_time) );
- wb_reg #(.ADDR(12),.DEFAULT(0))
+ wb_reg #(.ADDR(12),.DEFAULT(0),.WIDTH(16))
wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(pause_thresh) );
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build
index 30f65ab17..9293deca6 100755
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build
index 4be0aac1f..b9475baa2 100755
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
index 7d57542dc..b61d60d30 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
@@ -44,12 +44,12 @@ module simple_gemac_wrapper19_tb;
reg wb_stb=0, wb_cyc=0, wb_we=0;
wire wb_ack;
- reg [18:0] tx_f19_data=0;
+ reg [19:0] tx_f19_data=0;
reg tx_f19_src_rdy = 0;
wire tx_f19_dst_rdy;
- wire [35:0] rx_f36_data;
- wire rx_f36_src_rdy;
- wire rx_f36_dst_rdy = 1;
+ wire [35:0] rx_f19_data;
+ wire rx_f19_src_rdy;
+ wire rx_f19_dst_rdy = 1;
simple_gemac_wrapper19 simple_gemac_wrapper19
(.clk125(eth_clk), .reset(reset),
@@ -59,7 +59,7 @@ module simple_gemac_wrapper19_tb;
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
//.pause_req(pause_req), .pause_time(pause_time),
- .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+ .sys_clk(sys_clk), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
.tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
.wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
index 26a471a49..0aadc7e93 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
@@ -24,9 +24,6 @@ module simple_gemac_wrapper_tb;
wire [7:0] rx_data, tx_data;
- reg [15:0] pause_time;
- reg pause_req = 0;
-
wire GMII_RX_CLK = GMII_GTX_CLK;
reg [7:0] FORCE_DAT_ERR = 0;
@@ -47,7 +44,7 @@ module simple_gemac_wrapper_tb;
reg [35:0] tx_f36_data=0;
reg tx_f36_src_rdy = 0;
wire tx_f36_dst_rdy;
- wire rx_f36_data;
+ wire [35:0] rx_f36_data;
wire rx_f36_src_rdy;
wire rx_f36_dst_rdy = 1;
@@ -57,7 +54,6 @@ module simple_gemac_wrapper_tb;
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
- .pause_req(pause_req), .pause_time(pause_time),
.sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
.tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 04:01:08 +0000