1 files changed, 9 insertions, 4 deletions
diff --git a/fpga/usrp2/sdr_lib/round_reg.v b/fpga/usrp2/sdr_lib/round_reg.v
index aa0972dab..6f2e974d7 100644
--- a/fpga/usrp2/sdr_lib/round_reg.v
+++ b/fpga/usrp2/sdr_lib/round_reg.v
@@ -27,13 +27,18 @@ module round_reg
     parameter bits_out=0)
     (input clk,
      input [bits_in-1:0] in,
-     output reg [bits_out-1:0] out);
+     output reg [bits_out-1:0] out,
+     output reg [bits_in-bits_out:0] err);
 
    wire [bits_out-1:0] temp;
-
-   round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp));
+   wire [bits_in-bits_out:0] err_temp;
+   
+   round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp));
    
    always @(posedge clk)
      out <= temp;
+
+   always @(posedge clk)
+     err <= err_temp;
    
-endmodule // round
+endmodule // round_reg