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Diffstat (limited to 'fpga/usrp2/sdr_lib/add2.v')
| -rw-r--r-- | fpga/usrp2/sdr_lib/add2.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/fpga/usrp2/sdr_lib/add2.v b/fpga/usrp2/sdr_lib/add2.v new file mode 100644 index 000000000..dcca84fd3 --- /dev/null +++ b/fpga/usrp2/sdr_lib/add2.v @@ -0,0 +1,28 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module add2 + #(parameter WIDTH=16) + (input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output [WIDTH-1:0] sum); + + wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; + assign sum = sum_int[WIDTH:1]; // Note -- will have some bias + +endmodule // add2 |