diff options
Diffstat (limited to 'fpga/usrp2/gpmc')
| -rw-r--r-- | fpga/usrp2/gpmc/.gitignore | 2 | ||||
| -rw-r--r-- | fpga/usrp2/gpmc/Makefile.srcs | 14 | ||||
| -rw-r--r-- | fpga/usrp2/gpmc/cross_clock_reader.v | 44 | ||||
| -rw-r--r-- | fpga/usrp2/gpmc/fifo_to_gpmc.v | 159 | ||||
| -rw-r--r-- | fpga/usrp2/gpmc/gpmc.v | 196 | ||||
| -rw-r--r-- | fpga/usrp2/gpmc/gpmc_to_fifo.v | 157 | ||||
| -rw-r--r-- | fpga/usrp2/gpmc/gpmc_wb.v | 79 |
7 files changed, 651 insertions, 0 deletions
diff --git a/fpga/usrp2/gpmc/.gitignore b/fpga/usrp2/gpmc/.gitignore new file mode 100644 index 000000000..3e14fa4f7 --- /dev/null +++ b/fpga/usrp2/gpmc/.gitignore @@ -0,0 +1,2 @@ +*.gif + diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs new file mode 100644 index 000000000..4c6a1b4a2 --- /dev/null +++ b/fpga/usrp2/gpmc/Makefile.srcs @@ -0,0 +1,14 @@ +# +# Copyright 2010-2011 Ettus Research LLC +# + +################################################## +# GPMC Sources +################################################## +GPMC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpmc/, \ +cross_clock_reader.v \ +fifo_to_gpmc.v \ +gpmc.v \ +gpmc_to_fifo.v \ +gpmc_wb.v \ +)) diff --git a/fpga/usrp2/gpmc/cross_clock_reader.v b/fpga/usrp2/gpmc/cross_clock_reader.v new file mode 100644 index 000000000..a8366badc --- /dev/null +++ b/fpga/usrp2/gpmc/cross_clock_reader.v @@ -0,0 +1,44 @@ +// +// Copyright 2011-2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +module cross_clock_reader + #( + parameter WIDTH = 1, + parameter DEFAULT = 0 + ) + ( + input clk, input rst, + input [WIDTH-1:0] in, + output reg [WIDTH-1:0] out + ); + + reg [WIDTH-1:0] shadow0, shadow1; + + always @(posedge clk) begin + if (rst) begin + out <= DEFAULT; + shadow0 <= DEFAULT; + shadow1 <= DEFAULT; + end + else if (shadow0 == shadow1) begin + out <= shadow1; + end + shadow0 <= in; + shadow1 <= shadow0; + end + +endmodule //cross_clock_reader diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc.v b/fpga/usrp2/gpmc/fifo_to_gpmc.v new file mode 100644 index 000000000..42c71d2d6 --- /dev/null +++ b/fpga/usrp2/gpmc/fifo_to_gpmc.v @@ -0,0 +1,159 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +//////////////////////////////////////////////////////////////////////// +// FIFO to GPMC +// +// Reads frames from FIFO interface and writes them into BRAM pages. +// The GPMC is asynchronously alerted when a BRAM page has been filled. +// +// EM_CLK: +// A GPMC read transaction consists of two EM_CLK cycles (idle low). +// +// EM_OE: +// Output enable is actually the combination of ~NOE & ~NCS. +// The output enable is only active for the second rising edge, +// to ensure one edge per transaction to transition on. +// +// EM_D: +// The BRAM performs a read on the first rising edge into EM_D. +// Then, data will then be read on the next rising edge by GPMC. +// +// EM_A: +// On the first rising edge of EM_CLK, the address is held. +// On the second rising edge, the address is set for the next transaction. +//////////////////////////////////////////////////////////////////////// + +module fifo_to_gpmc + #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10) + (input clk, input reset, input clear, input arst, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + output [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_OE, + output reg data_available); + + //states for the GPMC side of things + wire [17:0] data_o; + reg gpmc_state; + reg [ADDR_WIDTH:1] addr; + reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr; + localparam GPMC_STATE_START = 0; + localparam GPMC_STATE_EMPTY = 1; + + //states for the FIFO side of things + reg fifo_state; + reg [ADDR_WIDTH-1:0] counter; + reg [PTR_WIDTH:0] fifo_ptr; + localparam FIFO_STATE_CLAIM = 0; + localparam FIFO_STATE_FILL = 1; + + //------------------------------------------------------------------ + // State machine to control the data from GPMC to BRAM + //------------------------------------------------------------------ + always @(posedge EM_CLK or posedge arst) begin + if (arst) begin + gpmc_state <= GPMC_STATE_START; + gpmc_ptr <= 0; + next_gpmc_ptr <= 0; + addr <= 0; + end + else if (EM_OE) begin + addr <= EM_A + 1; + case(gpmc_state) + + GPMC_STATE_START: begin + if (EM_A == 0) begin + gpmc_state <= GPMC_STATE_EMPTY; + next_gpmc_ptr <= gpmc_ptr + 1; + end + end + + GPMC_STATE_EMPTY: begin + if (EM_A == 10'h3ff) begin + gpmc_state <= GPMC_STATE_START; + gpmc_ptr <= next_gpmc_ptr; + end + end + + endcase //gpmc_state + end //EM_WE + end //always + + //------------------------------------------------------------------ + // High when the gpmc pointer has not caught up to the fifo pointer. + //------------------------------------------------------------------ + wire [PTR_WIDTH:0] safe_gpmc_ptr; + cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_gpmc_ptr + (.clk(clk), .rst(reset | clear), .in(gpmc_ptr), .out(safe_gpmc_ptr)); + + wire bram_available_to_fill = (fifo_ptr ^ (1 << PTR_WIDTH)) != safe_gpmc_ptr; + + //------------------------------------------------------------------ + // Glich free generation of data available signal: + // Data is available when the pointers dont match. + //------------------------------------------------------------------ + wire [PTR_WIDTH:0] safe_next_gpmc_ptr; + cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_next_gpmc_ptr + (.clk(clk), .rst(reset | clear), .in(next_gpmc_ptr), .out(safe_next_gpmc_ptr)); + + always @(posedge clk) + if (reset | clear) data_available <= 0; + else data_available <= safe_next_gpmc_ptr != fifo_ptr; + + //------------------------------------------------------------------ + // State machine to control the data from BRAM to FIFO + //------------------------------------------------------------------ + always @(posedge clk) begin + if (reset | clear) begin + fifo_state <= FIFO_STATE_CLAIM; + fifo_ptr <= 0; + counter <= 0; + end + else begin + case(fifo_state) + + FIFO_STATE_CLAIM: begin + if (bram_available_to_fill) fifo_state <= FIFO_STATE_FILL; + counter <= 0; + end + + FIFO_STATE_FILL: begin + if (src_rdy_i && dst_rdy_o && data_i[17]) begin + fifo_state <= FIFO_STATE_CLAIM; + fifo_ptr <= fifo_ptr + 1; + end + if (src_rdy_i && dst_rdy_o) begin + counter <= counter + 1; + end + end + + endcase //fifo_state + end + end //always + + assign dst_rdy_o = fifo_state == FIFO_STATE_FILL; + + //assign data from bram output + assign EM_D = data_o[15:0]; + + //instantiate dual ported bram for async read + write + ram_2port #(.DWIDTH(18),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram + (.clka(clk),.ena(1'b1),.wea(src_rdy_i && dst_rdy_o), + .addra({fifo_ptr[PTR_WIDTH-1:0], counter}),.dia(data_i),.doa(), + .clkb(EM_CLK),.enb(1'b1),.web(1'b0), + .addrb({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dib(18'h3ffff),.dob(data_o)); + +endmodule // fifo_to_gpmc diff --git a/fpga/usrp2/gpmc/gpmc.v b/fpga/usrp2/gpmc/gpmc.v new file mode 100644 index 000000000..8ecae4daf --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc.v @@ -0,0 +1,196 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +////////////////////////////////////////////////////////////////////////////////// + +module gpmc + #(parameter TXFIFOSIZE = 11, + parameter RXFIFOSIZE = 11, + parameter ADDR_WIDTH = 10, + parameter BUSDEBUG = 1) + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, + + // Wishbone signals + input wb_clk, input wb_rst, + output [ADDR_WIDTH:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + output tx_underrun, output rx_overrun, + input [7:0] test_rate, input [3:0] test_ctrl, + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + // these registers are used for the GPMC-to-FIFO interface + reg [15:0] em_d_reg; + reg [ADDR_WIDTH:1] em_a_reg; + reg [1:0] em_nbe_reg; + reg em_wait0_reg; + reg em_ncs4_reg; + reg em_ncs6_reg; + reg em_nwe_reg; + reg em_noe_reg; + + + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data; + wire tx18_src_rdy, tx18_dst_rdy; + wire [35:0] tx_data, txb_data; + wire tx_src_rdy, tx_dst_rdy; + wire txb_src_rdy, txb_dst_rdy; + + // Register signals to prevent Sequence errors (S-errors) from occuring + always @(negedge EM_CLK or posedge arst) begin + if (arst) begin + + em_d_reg <= 0; + em_a_reg <= 0; + em_nbe_reg <= 0; + em_wait0_reg <= 0; + em_ncs4_reg <= 0; + em_ncs6_reg <= 0; + em_nwe_reg <= 0; + em_noe_reg <= 0; + end + else begin + em_d_reg <= EM_D; + em_a_reg <= EM_A; + em_nbe_reg <= EM_NBE; + em_wait0_reg <= EM_WAIT0; + em_ncs4_reg <= EM_NCS4; + em_ncs6_reg <= EM_NCS6; + em_nwe_reg <= EM_NWE; + em_noe_reg <= EM_NOE; + end + end + + gpmc_to_fifo #(.ADDR_WIDTH(ADDR_WIDTH)) gpmc_to_fifo + (.EM_D(em_d_reg), .EM_A(em_a_reg), .EM_CLK(EM_CLK), .EM_WE(~em_ncs4_reg & ~em_nwe_reg), + .clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .arst(fifo_rst | clear_tx | arst), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .have_space(tx_have_space)); + + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy), + .f36_dataout(txb_data), .f36_src_rdy_o(txb_src_rdy), .f36_dst_rdy_i(txb_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_buffering( + .clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .datain(txb_data), .src_rdy_i(txb_src_rdy), .dst_rdy_o(txb_dst_rdy), + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) + ); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data; + wire rx18_src_rdy, rx18_dst_rdy; + wire [35:0] rx_data, rxb_data; + wire rx_src_rdy, rx_dst_rdy; + wire rxb_src_rdy, rxb_dst_rdy; + wire dummy; + + fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_buffering( + .clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), + .dataout(rxb_data), .src_rdy_o(rxb_src_rdy), .dst_rdy_i(rxb_dst_rdy) + ); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .f36_datain(rxb_data), .f36_src_rdy_i(rxb_src_rdy), .f36_dst_rdy_o(rxb_dst_rdy), + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); + + fifo_to_gpmc #(.ADDR_WIDTH(ADDR_WIDTH)) fifo_to_gpmc + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .arst(fifo_rst | clear_rx | arst), + .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), + .EM_D(EM_D_fifo), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS4 & ~EM_NOE), + .data_available(rx_have_data)); + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WE(~EM_NCS6 & ~EM_NWE), .EM_OE(~EM_NCS6 & ~EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + // //////////////////////////////////////////// + // Test support, traffic generator, loopback, etc. + + // RX side muxes test data into the same stream + wire [35:0] loopbackrx_data, testrx_data; + wire [35:0] loopbacktx_data, testtx_data; + wire loopbackrx_src_rdy, loopbackrx_dst_rdy; + wire loopbacktx_src_rdy, loopbacktx_dst_rdy; + wire sel_testtx = test_ctrl[0]; + + fifo36_mux rx_test_mux_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(loopbackrx_data), .src0_rdy_i(loopbackrx_src_rdy), .dst0_rdy_o(loopbackrx_dst_rdy), + .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + fifo_short #(.WIDTH(36)) loopback_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx), + .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy), + .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy)); + + // Crossbar used as a demux for switching TX stream to main DSP or to test logic + crossbar36 tx_crossbar_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_testtx), + .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy), + .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i), + .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) ); + + assign debug = { + EM_D, //16 + EM_A, //10 + EM_CLK, EM_NCS4, EM_NWE, EM_NOE, //4 + EM_NCS6, wb_ack_i + }; + +endmodule // gpmc diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo.v b/fpga/usrp2/gpmc/gpmc_to_fifo.v new file mode 100644 index 000000000..4aa55953a --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_to_fifo.v @@ -0,0 +1,157 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +//////////////////////////////////////////////////////////////////////// +// GPMC to FIFO +// +// Reads frames from BRAM pages and writes them into FIFO interface. +// The GPMC is asynchronously alerted when a BRAM page is available. +// +// EM_CLK: +// A GPMC read transaction consists of one EM_CLK cycle (idle low). +// +// EM_WE: +// Write enable is actually the combination of ~NWE & ~NCS. +// The write enable is active for the entire transaction. +// +// EM_D: +// Data is set on the rising edge and written into BRAM on the falling edge. +// +// EM_A: +// Address is set on the rising edge and read by BRAM on the falling edge. +//////////////////////////////////////////////////////////////////////// + +module gpmc_to_fifo + #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10) + (input [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_WE, + input clk, input reset, input clear, input arst, + output [17:0] data_o, output src_rdy_o, input dst_rdy_i, + output reg have_space); + + //states for the GPMC side of things + wire [17:0] data_i; + reg gpmc_state; + reg [ADDR_WIDTH:1] last_addr; + reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr; + localparam GPMC_STATE_START = 0; + localparam GPMC_STATE_FILL = 1; + + //states for the FIFO side of things + reg fifo_state; + reg [ADDR_WIDTH-1:0] counter; + reg [PTR_WIDTH:0] fifo_ptr; + localparam FIFO_STATE_CLAIM = 0; + localparam FIFO_STATE_EMPTY = 1; + + //------------------------------------------------------------------ + // State machine to control the data from GPMC to BRAM + //------------------------------------------------------------------ + always @(negedge EM_CLK or posedge arst) begin + if (arst) begin + gpmc_state <= GPMC_STATE_START; + gpmc_ptr <= 0; + next_gpmc_ptr <= 0; + end + else if (EM_WE) begin + case(gpmc_state) + + GPMC_STATE_START: begin + if (EM_A == 0) begin + gpmc_state <= GPMC_STATE_FILL; + last_addr <= {EM_D[ADDR_WIDTH-2:0], 1'b0} - 1'b1; + next_gpmc_ptr <= gpmc_ptr + 1; + end + end + + GPMC_STATE_FILL: begin + if (data_i[17]) begin + gpmc_state <= GPMC_STATE_START; + gpmc_ptr <= next_gpmc_ptr; + end + end + + endcase //gpmc_state + end //EM_WE + end //always + + //------------------------------------------------------------------ + // A block ram is available to empty when the pointers dont match. + //------------------------------------------------------------------ + wire [PTR_WIDTH:0] safe_gpmc_ptr; + cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_gpmc_ptr + (.clk(clk), .rst(reset | clear), .in(gpmc_ptr), .out(safe_gpmc_ptr)); + + wire bram_available_to_empty = safe_gpmc_ptr != fifo_ptr; + + //------------------------------------------------------------------ + // Glich free generation of have space signal: + // High when the fifo pointer has not caught up to the gpmc pointer. + //------------------------------------------------------------------ + wire [PTR_WIDTH:0] safe_next_gpmc_ptr; + cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_next_gpmc_ptr + (.clk(clk), .rst(reset | clear), .in(next_gpmc_ptr), .out(safe_next_gpmc_ptr)); + + always @(posedge clk) + if (reset | clear) have_space <= 0; + else have_space <= (fifo_ptr ^ (1 << PTR_WIDTH)) != safe_next_gpmc_ptr; + + //------------------------------------------------------------------ + // State machine to control the data from BRAM to FIFO + //------------------------------------------------------------------ + always @(posedge clk) begin + if (reset | clear) begin + fifo_state <= FIFO_STATE_CLAIM; + fifo_ptr <= 0; + counter <= 0; + end + else begin + case(fifo_state) + + FIFO_STATE_CLAIM: begin + if (bram_available_to_empty) fifo_state <= FIFO_STATE_EMPTY; + counter <= 0; + end + + FIFO_STATE_EMPTY: begin + if (src_rdy_o && dst_rdy_i && data_o[17]) begin + fifo_state <= FIFO_STATE_CLAIM; + fifo_ptr <= fifo_ptr + 1; + end + if (src_rdy_o && dst_rdy_i) begin + counter <= counter + 1; + end + end + + endcase //fifo_state + end + end //always + + assign src_rdy_o = fifo_state == FIFO_STATE_EMPTY; + + //assign data and frame bits to bram input + assign data_i[15:0] = EM_D; + assign data_i[16] = (gpmc_state == GPMC_STATE_START); + assign data_i[17] = (EM_A == last_addr); + + //instantiate dual ported bram for async read + write + ram_2port #(.DWIDTH(18),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram + (.clka(~EM_CLK),.ena(1'b1),.wea(EM_WE), + .addra({gpmc_ptr[PTR_WIDTH-1:0], EM_A}),.dia(data_i),.doa(), + .clkb(~clk),.enb(1'b1),.web(1'b0), + .addrb({fifo_ptr[PTR_WIDTH-1:0], counter}),.dib(18'h3ffff),.dob(data_o)); + +endmodule // gpmc_to_fifo diff --git a/fpga/usrp2/gpmc/gpmc_wb.v b/fpga/usrp2/gpmc/gpmc_wb.v new file mode 100644 index 000000000..4d368ca94 --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_wb.v @@ -0,0 +1,79 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + + +module gpmc_wb + (input EM_CLK, input [15:0] EM_D_in, output [15:0] EM_D_out, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WE, input EM_OE, + + input wb_clk, input wb_rst, + output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i); + + // //////////////////////////////////////////// + // Control Path, Wishbone bus bridge (wb master) + reg [1:0] we_del, oe_del; + + // Synchronize the async control signals + always @(posedge wb_clk) + if (wb_rst) begin + we_del <= 2'b0; + oe_del <= 2'b0; + end + else begin + we_del <= { we_del[0], EM_WE }; + oe_del <= { oe_del[0], EM_OE }; + end + + wire writing = we_del == 2'b01; + wire reading = oe_del == 2'b01; + + always @(posedge wb_clk) + if(writing || reading) + wb_adr_o <= { EM_A, 1'b0 }; + + always @(posedge wb_clk) + if(writing) + begin + wb_dat_mosi <= EM_D_in; + wb_sel_o <= ~EM_NBE; + end + + reg [15:0] EM_D_hold; + + always @(posedge wb_clk) + if(wb_ack_i) + EM_D_hold <= wb_dat_miso; + + assign EM_D_out = wb_ack_i ? wb_dat_miso : EM_D_hold; + + assign wb_cyc_o = wb_stb_o; + + always @(posedge wb_clk) + if(writing) + wb_we_o <= 1; + else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... + wb_we_o <= 0; + + always @(posedge wb_clk) + if(writing || reading) + wb_stb_o <= 1; + else if(wb_ack_i) + wb_stb_o <= 0; + +endmodule // gpmc_wb |