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-rw-r--r--fpga/usrp2/gpmc/.gitignore2
-rw-r--r--fpga/usrp2/gpmc/Makefile.srcs13
-rw-r--r--fpga/usrp2/gpmc/cross_clock_reader.v46
-rw-r--r--fpga/usrp2/gpmc/fifo_to_gpmc.v160
-rw-r--r--fpga/usrp2/gpmc/gpmc.v167
-rw-r--r--fpga/usrp2/gpmc/gpmc_to_fifo.v177
6 files changed, 565 insertions, 0 deletions
diff --git a/fpga/usrp2/gpmc/.gitignore b/fpga/usrp2/gpmc/.gitignore
new file mode 100644
index 000000000..3e14fa4f7
--- /dev/null
+++ b/fpga/usrp2/gpmc/.gitignore
@@ -0,0 +1,2 @@
+*.gif
+
diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs
new file mode 100644
index 000000000..39b37db58
--- /dev/null
+++ b/fpga/usrp2/gpmc/Makefile.srcs
@@ -0,0 +1,13 @@
+#
+# Copyright 2010-2012 Ettus Research LLC
+#
+
+##################################################
+# GPMC Sources
+##################################################
+GPMC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpmc/, \
+cross_clock_reader.v \
+fifo_to_gpmc.v \
+gpmc.v \
+gpmc_to_fifo.v \
+))
diff --git a/fpga/usrp2/gpmc/cross_clock_reader.v b/fpga/usrp2/gpmc/cross_clock_reader.v
new file mode 100644
index 000000000..b4cdb79c5
--- /dev/null
+++ b/fpga/usrp2/gpmc/cross_clock_reader.v
@@ -0,0 +1,46 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+module cross_clock_reader
+ #(
+ parameter WIDTH = 1,
+ parameter DEFAULT = 0
+ )
+ (
+ input clk, input rst,
+ input [WIDTH-1:0] in,
+ output reg [WIDTH-1:0] out
+ );
+
+ reg [WIDTH-1:0] shadow0, shadow1;
+ reg [2:0] count;
+
+ always @(posedge clk) begin
+ if (rst) begin
+ out <= DEFAULT;
+ shadow0 <= DEFAULT;
+ shadow1 <= DEFAULT;
+ count <= 0;
+ end
+ else if (shadow0 == shadow1) count <= count + 1;
+ else count <= 0;
+ shadow0 <= in;
+ shadow1 <= shadow0;
+ if (count == 3'b111) out <= shadow1;
+ end
+
+endmodule //cross_clock_reader
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc.v b/fpga/usrp2/gpmc/fifo_to_gpmc.v
new file mode 100644
index 000000000..26443a702
--- /dev/null
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc.v
@@ -0,0 +1,160 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+////////////////////////////////////////////////////////////////////////
+// FIFO to GPMC
+//
+// Reads frames from FIFO interface and writes them into BRAM pages.
+// The GPMC is asynchronously alerted when a BRAM page has been filled.
+//
+// EM_CLK:
+// A GPMC read transaction consists of two EM_CLK cycles (idle low).
+//
+// EM_OE:
+// Output enable is actually the combination of ~NOE & ~NCS.
+// The output enable is only active for the second rising edge,
+// to ensure one edge per transaction to transition on.
+//
+// EM_D:
+// The BRAM performs a read on the first rising edge into EM_D.
+// Then, data will then be read on the next rising edge by GPMC.
+//
+// EM_A:
+// On the first rising edge of EM_CLK, the address is held.
+// On the second rising edge, the address is set for the next transaction.
+////////////////////////////////////////////////////////////////////////
+
+module fifo_to_gpmc
+ #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter LAST_ADDR = 10'h3ff)
+ (input clk, input reset, input clear, input arst,
+ input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
+ output [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_OE,
+ output reg data_available);
+
+ //states for the GPMC side of things
+ wire [17:0] data_o;
+ reg gpmc_state;
+ reg [ADDR_WIDTH:1] addr;
+ reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr;
+ localparam GPMC_STATE_START = 0;
+ localparam GPMC_STATE_EMPTY = 1;
+
+ //states for the FIFO side of things
+ reg fifo_state;
+ reg [ADDR_WIDTH-1:0] counter;
+ reg [PTR_WIDTH:0] fifo_ptr;
+ localparam FIFO_STATE_CLAIM = 0;
+ localparam FIFO_STATE_FILL = 1;
+
+ //------------------------------------------------------------------
+ // State machine to control the data from GPMC to BRAM
+ //------------------------------------------------------------------
+ always @(posedge EM_CLK or posedge arst) begin
+ if (arst) begin
+ gpmc_state <= GPMC_STATE_START;
+ gpmc_ptr <= 0;
+ next_gpmc_ptr <= 0;
+ addr <= 0;
+ end
+ else if (EM_OE) begin
+ addr <= EM_A + 1;
+ case(gpmc_state)
+
+ GPMC_STATE_START: begin
+ if (EM_A == 0) begin
+ gpmc_state <= GPMC_STATE_EMPTY;
+ next_gpmc_ptr <= gpmc_ptr + 1;
+ end
+ end
+
+ GPMC_STATE_EMPTY: begin
+ if (addr == LAST_ADDR) begin
+ gpmc_state <= GPMC_STATE_START;
+ gpmc_ptr <= next_gpmc_ptr;
+ addr <= 0;
+ end
+ end
+
+ endcase //gpmc_state
+ end //EM_OE
+ end //always
+
+ //------------------------------------------------------------------
+ // High when the gpmc pointer has not caught up to the fifo pointer.
+ //------------------------------------------------------------------
+ wire [PTR_WIDTH:0] safe_gpmc_ptr;
+ cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_gpmc_ptr
+ (.clk(clk), .rst(reset | clear), .in(gpmc_ptr), .out(safe_gpmc_ptr));
+
+ wire bram_available_to_fill = (fifo_ptr ^ (1 << PTR_WIDTH)) != safe_gpmc_ptr;
+
+ //------------------------------------------------------------------
+ // Glich free generation of data available signal:
+ // Data is available when the pointers dont match.
+ //------------------------------------------------------------------
+ wire [PTR_WIDTH:0] safe_next_gpmc_ptr;
+ cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_next_gpmc_ptr
+ (.clk(clk), .rst(reset | clear), .in(next_gpmc_ptr), .out(safe_next_gpmc_ptr));
+
+ always @(posedge clk)
+ if (reset | clear) data_available <= 0;
+ else data_available <= safe_next_gpmc_ptr != fifo_ptr;
+
+ //------------------------------------------------------------------
+ // State machine to control the data from BRAM to FIFO
+ //------------------------------------------------------------------
+ always @(posedge clk) begin
+ if (reset | clear) begin
+ fifo_state <= FIFO_STATE_CLAIM;
+ fifo_ptr <= 0;
+ counter <= 0;
+ end
+ else begin
+ case(fifo_state)
+
+ FIFO_STATE_CLAIM: begin
+ if (bram_available_to_fill) fifo_state <= FIFO_STATE_FILL;
+ counter <= 0;
+ end
+
+ FIFO_STATE_FILL: begin
+ if (src_rdy_i && dst_rdy_o && data_i[17]) begin
+ fifo_state <= FIFO_STATE_CLAIM;
+ fifo_ptr <= fifo_ptr + 1;
+ end
+ if (src_rdy_i && dst_rdy_o) begin
+ counter <= counter + 1;
+ end
+ end
+
+ endcase //fifo_state
+ end
+ end //always
+
+ assign dst_rdy_o = fifo_state == FIFO_STATE_FILL;
+
+ //assign data from bram output
+ assign EM_D = data_o[15:0];
+
+ //instantiate dual ported bram for async read + write
+ ram_2port #(.DWIDTH(18),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
+ (.clka(clk),.ena(1'b1),.wea(src_rdy_i && dst_rdy_o),
+ .addra({fifo_ptr[PTR_WIDTH-1:0], counter}),.dia(data_i),.doa(),
+ .clkb(EM_CLK),.enb(1'b1),.web(1'b0),
+ .addrb({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dib(18'h3ffff),.dob(data_o));
+
+endmodule // fifo_to_gpmc
diff --git a/fpga/usrp2/gpmc/gpmc.v b/fpga/usrp2/gpmc/gpmc.v
new file mode 100644
index 000000000..2f22889cc
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc.v
@@ -0,0 +1,167 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+//////////////////////////////////////////////////////////////////////////////////
+
+module gpmc
+ #(parameter TXFIFOSIZE = 11,
+ parameter RXFIFOSIZE = 11,
+ parameter ADDR_WIDTH = 10,
+ parameter BUSDEBUG = 1)
+ (// GPMC signals
+ input arst,
+ input EM_CLK, inout [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input [1:0] EM_NBE,
+ input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+
+ // GPIOs for FIFO signalling
+ output rx_have_data, output tx_have_space, output resp_have_data,
+
+ // FIFO interface
+ input fifo_clk, input fifo_rst,
+ output [35:0] tx_data, output tx_src_rdy, input tx_dst_rdy,
+ input [35:0] rx_data, input rx_src_rdy, output rx_dst_rdy,
+ output [35:0] ctrl_data, output ctrl_src_rdy, input ctrl_dst_rdy,
+ input [35:0] resp_data, input resp_src_rdy, output resp_dst_rdy,
+
+ output [31:0] debug
+ );
+
+ wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+ wire [15:0] EM_D_data;
+ wire [15:0] EM_D_ctrl;
+
+ assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_data : EM_D_ctrl;
+
+ // CS4 is RAM_2PORT for DATA PATH (high-speed data)
+ // Writes go into one RAM, reads come from the other
+ // CS6 is for CONTROL PATH (slow)
+
+ // ////////////////////////////////////////////
+ // TX Data Path
+
+ wire [17:0] tx18_data;
+ wire tx18_src_rdy, tx18_dst_rdy;
+ wire [35:0] txb_data;
+ wire txb_src_rdy, txb_dst_rdy;
+
+ gpmc_to_fifo #(.ADDR_WIDTH(10), .LAST_ADDR(10'h3ff), .PTR_WIDTH(2)) gpmc_to_fifo
+ (.EM_D(EM_D), .EM_A(EM_A[10:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS4 & ~EM_NWE),
+ .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
+ .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
+ .have_space(tx_have_space));
+
+ fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+ .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy),
+ .f36_dataout(txb_data), .f36_src_rdy_o(txb_src_rdy), .f36_dst_rdy_i(txb_dst_rdy));
+
+ fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_buffering(
+ .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+ .datain(txb_data), .src_rdy_i(txb_src_rdy), .dst_rdy_o(txb_dst_rdy),
+ .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)
+ );
+
+ // ////////////////////////////////////////////
+ // RX Data Path
+
+ wire [17:0] rx18_data;
+ wire rx18_src_rdy, rx18_dst_rdy;
+ wire [35:0] rxb_data;
+ wire rxb_src_rdy, rxb_dst_rdy;
+ wire dummy;
+
+ fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_buffering(
+ .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+ .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
+ .dataout(rxb_data), .src_rdy_o(rxb_src_rdy), .dst_rdy_i(rxb_dst_rdy)
+ );
+
+ fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+ .f36_datain(rxb_data), .f36_src_rdy_i(rxb_src_rdy), .f36_dst_rdy_o(rxb_dst_rdy),
+ .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
+
+ fifo_to_gpmc #(.ADDR_WIDTH(ADDR_WIDTH), .LAST_ADDR(10'h3ff)) fifo_to_gpmc
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
+ .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy),
+ .EM_D(EM_D_data), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS4 & ~EM_NOE),
+ .data_available(rx_have_data));
+
+ // ////////////////////////////////////////////
+ // Control path on CS6
+
+ // ////////////////////////////////////////////////////////////////////
+ // CTRL TX Data Path
+
+ wire [17:0] ctrl18_data;
+ wire ctrl18_src_rdy, ctrl18_dst_rdy;
+ wire [35:0] ctrlb_data;
+ wire ctrlb_src_rdy, ctrlb_dst_rdy;
+
+ gpmc_to_fifo #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) ctrl_gpmc_to_fifo
+ (.EM_D(EM_D), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS6 & ~EM_NWE),
+ .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
+ .data_o(ctrl18_data), .src_rdy_o(ctrl18_src_rdy), .dst_rdy_i(ctrl18_dst_rdy),
+ .have_space(/*always*/));
+
+ fifo19_to_fifo36 #(.LE(1)) ctrl_f19_to_f36 // Little endian because ARM is LE
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+ .f19_datain({1'b0,ctrl18_data}), .f19_src_rdy_i(ctrl18_src_rdy), .f19_dst_rdy_o(ctrl18_dst_rdy),
+ .f36_dataout(ctrlb_data), .f36_src_rdy_o(ctrlb_src_rdy), .f36_dst_rdy_i(ctrlb_dst_rdy));
+
+ fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_buffering(
+ .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+ .datain(ctrlb_data), .src_rdy_i(ctrlb_src_rdy), .dst_rdy_o(ctrlb_dst_rdy),
+ .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)
+ );
+
+ // ////////////////////////////////////////////
+ // CTRL RX Data Path
+
+ wire [17:0] resp18_data;
+ wire resp18_src_rdy, resp18_dst_rdy;
+ wire [35:0] respb_data;
+ wire respb_src_rdy, respb_dst_rdy;
+ wire resp_dummy;
+
+ fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_buffering(
+ .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+ .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy),
+ .dataout(respb_data), .src_rdy_o(respb_src_rdy), .dst_rdy_i(respb_dst_rdy)
+ );
+
+ fifo36_to_fifo19 #(.LE(1)) resp_f36_to_f19 // Little endian because ARM is LE
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
+ .f36_datain(respb_data), .f36_src_rdy_i(respb_src_rdy), .f36_dst_rdy_o(respb_dst_rdy),
+ .f19_dataout({resp_dummy,resp18_data}), .f19_src_rdy_o(resp18_src_rdy), .f19_dst_rdy_i(resp18_dst_rdy) );
+
+ fifo_to_gpmc #(.PTR_WIDTH(5), .ADDR_WIDTH(5), .LAST_ADDR(5'h0f)) resp_fifo_to_gpmc
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
+ .data_i(resp18_data), .src_rdy_i(resp18_src_rdy), .dst_rdy_o(resp18_dst_rdy),
+ .EM_D(EM_D_ctrl), .EM_A(EM_A[5:1]), .EM_CLK(EM_CLK), .EM_OE(~EM_NCS6 & ~EM_NOE),
+ .data_available(resp_have_data));
+//*
+ assign debug = {
+ EM_D,
+ //resp18_data[15:0], //16
+ EM_A, //10
+ //resp18_data[17:16], resp18_src_rdy, resp18_dst_rdy, //4
+ EM_NCS4, EM_NCS6, EM_NWE, EM_NOE, //4
+ EM_CLK, resp_have_data //2
+ };
+//*/
+endmodule // gpmc
diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo.v b/fpga/usrp2/gpmc/gpmc_to_fifo.v
new file mode 100644
index 000000000..d1897faec
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_to_fifo.v
@@ -0,0 +1,177 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+////////////////////////////////////////////////////////////////////////
+// GPMC to FIFO
+//
+// Reads frames from BRAM pages and writes them into FIFO interface.
+// The GPMC is asynchronously alerted when a BRAM page is available.
+//
+// EM_CLK:
+// A GPMC write transaction consists of one EM_CLK cycle (idle low).
+//
+// EM_WE:
+// Write enable is actually the combination of ~NWE & ~NCS.
+// The write enable is active for the entire transaction.
+//
+// EM_D:
+// Data is set on the rising edge and written into BRAM on the falling edge.
+//
+// EM_A:
+// Address is set on the rising edge and read by BRAM on the falling edge.
+////////////////////////////////////////////////////////////////////////
+
+module gpmc_to_fifo
+ #(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter LAST_ADDR = 10'h3ff)
+ (input [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_WE,
+ input clk, input reset, input clear, input arst,
+ output [17:0] data_o, output src_rdy_o, input dst_rdy_i,
+ output reg have_space);
+
+ //states for the GPMC side of things
+ reg gpmc_state;
+ reg [ADDR_WIDTH:1] addr;
+ reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr;
+ localparam GPMC_STATE_START = 0;
+ localparam GPMC_STATE_FILL = 1;
+
+ //states for the FIFO side of things
+ reg [1:0] fifo_state;
+ reg [ADDR_WIDTH-1:0] counter;
+ reg [ADDR_WIDTH-1:0] last_counter;
+ reg [ADDR_WIDTH-1:0] last_xfer;
+ reg [PTR_WIDTH:0] fifo_ptr;
+ localparam FIFO_STATE_CLAIM = 0;
+ localparam FIFO_STATE_EMPTY = 1;
+ localparam FIFO_STATE_PRE = 2;
+
+ //------------------------------------------------------------------
+ // State machine to control the data from GPMC to BRAM
+ //------------------------------------------------------------------
+ always @(negedge EM_CLK or posedge arst) begin
+ if (arst) begin
+ gpmc_state <= GPMC_STATE_START;
+ gpmc_ptr <= 0;
+ next_gpmc_ptr <= 0;
+ addr <= 0;
+ end
+ else if (EM_WE) begin
+ addr <= EM_A + 1;
+ case(gpmc_state)
+
+ GPMC_STATE_START: begin
+ if (EM_A == 0) begin
+ gpmc_state <= GPMC_STATE_FILL;
+ next_gpmc_ptr <= gpmc_ptr + 1;
+ end
+ end
+
+ GPMC_STATE_FILL: begin
+ if (addr == LAST_ADDR) begin
+ gpmc_state <= GPMC_STATE_START;
+ gpmc_ptr <= next_gpmc_ptr;
+ addr <= 0;
+ end
+ end
+
+ endcase //gpmc_state
+ end //EM_WE
+ end //always
+
+ //------------------------------------------------------------------
+ // A block ram is available to empty when the pointers dont match.
+ //------------------------------------------------------------------
+ wire [PTR_WIDTH:0] safe_gpmc_ptr;
+ cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_gpmc_ptr
+ (.clk(clk), .rst(reset | clear), .in(gpmc_ptr), .out(safe_gpmc_ptr));
+
+ wire bram_available_to_empty = safe_gpmc_ptr != fifo_ptr;
+
+ //------------------------------------------------------------------
+ // Glich free generation of have space signal:
+ // High when the fifo pointer has not caught up to the gpmc pointer.
+ //------------------------------------------------------------------
+ wire [PTR_WIDTH:0] safe_next_gpmc_ptr;
+ cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_next_gpmc_ptr
+ (.clk(clk), .rst(reset | clear), .in(next_gpmc_ptr), .out(safe_next_gpmc_ptr));
+
+ wire [PTR_WIDTH:0] fifo_ptr_next = fifo_ptr + 1;
+ always @(posedge clk)
+ if (reset | clear) have_space <= 0;
+ else have_space <= (fifo_ptr ^ (1 << PTR_WIDTH)) != safe_next_gpmc_ptr;
+
+ //------------------------------------------------------------------
+ // State machine to control the data from BRAM to FIFO
+ //------------------------------------------------------------------
+ always @(posedge clk) begin
+ if (reset | clear) begin
+ fifo_state <= FIFO_STATE_CLAIM;
+ fifo_ptr <= 0;
+ counter <= 0;
+ end
+ else begin
+ case(fifo_state)
+
+ FIFO_STATE_CLAIM: begin
+ if (bram_available_to_empty && data_o[16]) fifo_state <= FIFO_STATE_PRE;
+ counter <= 0;
+ end
+
+ FIFO_STATE_PRE: begin
+ fifo_state <= FIFO_STATE_EMPTY;
+ counter <= counter + 1;
+ end
+
+ FIFO_STATE_EMPTY: begin
+ if (src_rdy_o && dst_rdy_i && data_o[17]) begin
+ fifo_state <= FIFO_STATE_CLAIM;
+ fifo_ptr <= fifo_ptr + 1;
+ counter <= 0;
+ end
+ else if (src_rdy_o && dst_rdy_i) begin
+ counter <= counter + 1;
+ end
+ end
+
+ endcase //fifo_state
+ end
+ end //always
+
+ wire enable = (fifo_state != FIFO_STATE_EMPTY) || dst_rdy_i;
+
+ assign src_rdy_o = fifo_state == FIFO_STATE_EMPTY;
+
+ //instantiate dual ported bram for async read + write
+ ram_2port #(.DWIDTH(16),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
+ (.clka(~EM_CLK),.ena(1'b1),.wea(EM_WE),
+ .addra({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dia(EM_D),.doa(),
+ .clkb(clk),.enb(enable),.web(1'b0),
+ .addrb({fifo_ptr[PTR_WIDTH-1:0], counter}),.dib(18'h3ffff),.dob(data_o[15:0]));
+
+ //store the vita length -> last xfer count
+ always @(posedge clk) begin
+ if (src_rdy_o && dst_rdy_i && data_o[16]) begin
+ last_xfer <= {data_o[ADDR_WIDTH-2:0], 1'b0};
+ end
+ end
+
+ //logic for start and end of frame
+ always @(posedge clk) if (enable) last_counter <= counter;
+ assign data_o[17] = !data_o[16] && ((last_counter + 1'b1) == last_xfer);
+ assign data_o[16] = last_counter == 0;
+
+endmodule // gpmc_to_fifo
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