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-rw-r--r--fpga/usrp2/gpmc/fifo_to_gpmc_async.v5
1 files changed, 0 insertions, 5 deletions
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
index cf8b6e861..9a8e37ce9 100644
--- a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -1,9 +1,4 @@
-// Assumes an asynchronous GPMC cycle
-// If a packet bigger or smaller than we are told is sent, behavior is undefined.
-// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
-// If there is a bus error, we should be reset
-
module fifo_to_gpmc_async
(input clk, input reset, input clear,
input [17:0] data_i, input src_rdy_i, output dst_rdy_o,