diff options
Diffstat (limited to 'fpga/usrp2/gpif')
| -rw-r--r-- | fpga/usrp2/gpif/Makefile.srcs | 14 | ||||
| -rw-r--r-- | fpga/usrp2/gpif/gpif.v | 257 | ||||
| -rw-r--r-- | fpga/usrp2/gpif/gpif_rd.v | 111 | ||||
| -rw-r--r-- | fpga/usrp2/gpif/gpif_tb.v | 142 | ||||
| -rw-r--r-- | fpga/usrp2/gpif/gpif_wr.v | 95 | ||||
| -rw-r--r-- | fpga/usrp2/gpif/gpif_wr_tb.v | 110 | ||||
| -rw-r--r-- | fpga/usrp2/gpif/packet_reframer.v | 79 | ||||
| -rw-r--r-- | fpga/usrp2/gpif/packet_splitter.v | 123 | ||||
| -rw-r--r-- | fpga/usrp2/gpif/packet_splitter_tb.v | 137 |
9 files changed, 1068 insertions, 0 deletions
diff --git a/fpga/usrp2/gpif/Makefile.srcs b/fpga/usrp2/gpif/Makefile.srcs new file mode 100644 index 000000000..bf2b7f74d --- /dev/null +++ b/fpga/usrp2/gpif/Makefile.srcs @@ -0,0 +1,14 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# SERDES Sources +################################################## +GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \ +gpif.v \ +gpif_wr.v \ +gpif_rd.v \ +packet_reframer.v \ +packet_splitter.v \ +)) diff --git a/fpga/usrp2/gpif/gpif.v b/fpga/usrp2/gpif/gpif.v new file mode 100644 index 000000000..51d6e8ba9 --- /dev/null +++ b/fpga/usrp2/gpif/gpif.v @@ -0,0 +1,257 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +////////////////////////////////////////////////////////////////////////////////// + +module gpif + #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) + (// GPIF signals + input gpif_clk, input gpif_rst, + inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, + output [2:0] gpif_misc, + + // Wishbone signals + input wb_clk, input wb_rst, + output [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + input [7:0] triggers, + + // FIFO interface + input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o, + + output tx_underrun, output rx_overrun, + input [7:0] frames_per_packet, input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl, + output [31:0] debug0, output [31:0] debug1 + ); + + wire WR = gpif_ctl[0]; + wire RD = gpif_ctl[1]; + wire OE = gpif_ctl[2]; + wire EP = gpif_ctl[3]; + + wire CF, CE, DF, DE; + + assign gpif_rdy = { CF, CE, DF, DE }; + + wire [15:0] gpif_d_out; + assign gpif_d = OE ? gpif_d_out : 16'bz; + + wire [15:0] gpif_d_copy = gpif_d; + + wire [31:0] debug_rd, debug_wr, debug_split0, debug_split1; + + // //////////////////////////////////////////////////////////////////// + // TX Data Path + + wire [18:0] tx19_data; + wire tx19_src_rdy, tx19_dst_rdy; + wire [35:0] tx36_data, tx_data; + wire tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy; + + wire [18:0] ctrl_data; + wire ctrl_src_rdy, ctrl_dst_rdy; + + gpif_wr gpif_wr + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_d), .gpif_wr(WR), .gpif_ep(EP), + .gpif_full_d(DF), .gpif_full_c(CF), + + .sys_clk(fifo_clk), .sys_rst(fifo_rst), + .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy), + .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), + .debug(debug_wr) ); + + // join vita packets which are longer than one frame, drop frame padding + wire [18:0] refr_data; + wire refr_src_rdy, refr_dst_rdy; + + packet_reframer tx_packet_reframer + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(tx19_data), .src_rdy_i(tx19_src_rdy), .dst_rdy_o(tx19_dst_rdy), + .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy)); + + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy), + .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [35:0] rx36_data, rx_data; + wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy; + wire [18:0] rx19_data, splt_data; + wire rx19_src_rdy, rx19_dst_rdy, splt_src_rdy, splt_dst_rdy; + wire [18:0] resp_data, resp_int1, resp_int2; + wire resp_src_rdy, resp_dst_rdy; + wire resp_src_rdy_int1, resp_dst_rdy_int1, resp_src_rdy_int2, resp_dst_rdy_int2; + + fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), + .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), + .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); + + packet_splitter #(.FRAME_LEN(256)) packet_splitter + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .frames_per_packet(frames_per_packet), + .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), + .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy), + .debug0(debug_split0), .debug1(debug_split1)); + + gpif_rd gpif_rd + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP), + .gpif_empty_d(DE), .gpif_empty_c(CE), .gpif_flush(gpif_misc[0]), + + .sys_clk(fifo_clk), .sys_rst(fifo_rst), + .data_i(splt_data), .src_rdy_i(splt_src_rdy), .dst_rdy_o(splt_dst_rdy), + .resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), + .debug(debug_rd) ); + + // //////////////////////////////////////////////////////////////////// + // FIFO to Wishbone interface + + fifo_to_wb fifo_to_wb + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), + .data_o(resp_int1), .src_rdy_o(resp_src_rdy_int1), .dst_rdy_i(resp_dst_rdy_int1), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o), + .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i), + .triggers(triggers), + .debug0(), .debug1()); + + wire [18:0] tx_err19_data; + wire tx_err19_src_rdy, tx_err19_dst_rdy; + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19_txerr + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .f36_datain(tx_err_data_i), .f36_src_rdy_i(tx_err_src_rdy_i), .f36_dst_rdy_o(tx_err_dst_rdy_o), + .f19_dataout(tx_err19_data), .f19_src_rdy_o(tx_err19_src_rdy), .f19_dst_rdy_i(tx_err19_dst_rdy) ); + + fifo19_mux #(.prio(0)) mux_err_stream + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .data0_i(resp_int1), .src0_rdy_i(resp_src_rdy_int1), .dst0_rdy_o(resp_dst_rdy_int1), + .data1_i(tx_err19_data), .src1_rdy_i(tx_err19_src_rdy), .dst1_rdy_o(tx_err19_dst_rdy), + .data_o(resp_int2), .src_rdy_o(resp_src_rdy_int2), .dst_rdy_i(resp_dst_rdy_int2)); + + fifo19_pad #(.LENGTH(16)) fifo19_pad + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .data_i(resp_int2), .src_rdy_i(resp_src_rdy_int2), .dst_rdy_o(resp_dst_rdy_int2), + .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); + + // //////////////////////////////////////////////////////////////////// + // Debug support, timed and loopback + // RX side muxes test data into the same stream + wire [35:0] timedrx_data, loopbackrx_data, testrx_data; + wire [35:0] timedtx_data, loopbacktx_data, testtx_data; + wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy, + testrx_src_rdy, testrx_dst_rdy; + wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy, + testtx_src_rdy, testtx_dst_rdy; + wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; + + wire [31:0] total, crc_err, seq_err, len_err; + wire sel_testtx = test_ctrl[0]; + wire sel_loopbacktx = test_ctrl[1]; + wire pkt_src_enable = test_ctrl[2]; + wire pkt_sink_enable = test_ctrl[3]; + + fifo36_mux rx_test_mux_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy), + .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy), + .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy)); + + fifo36_mux rx_test_mux_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy), + .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + fifo_short #(.WIDTH(36)) loopback_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx), + .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy), + .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy)); + + // Crossbar used as a demux for switching TX stream to main DSP or to test logic + crossbar36 tx_crossbar_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_testtx), + .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy), + .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i), + .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) ); + + crossbar36 tx_crossbar_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_loopbacktx), + .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy), + .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy), + .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) ); + + // Fixed rate TX traffic consumer + fifo_pacer tx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable), + .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), + .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // Fixed rate RX traffic generator + vita_pkt_gen pktgen + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .len(test_len), + .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable), + .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), + .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + + // //////////////////////////////////////////// + // DEBUG + + //assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], + // gpif_d_copy[15:0] }; + + //assign debug1 = { { debug_rd[15:8] }, + // { debug_rd[7:0] }, + // { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, + // { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + + assign debug0 = { gpif_ctl[3:0], gpif_rdy[3:0], debug_split0[23:0] }; + assign debug1 = { gpif_misc[0], debug_rd[14:0], debug_split1[15:8], debug_split1[7:0] }; +endmodule // gpif diff --git a/fpga/usrp2/gpif/gpif_rd.v b/fpga/usrp2/gpif/gpif_rd.v new file mode 100644 index 000000000..b05c3cfb6 --- /dev/null +++ b/fpga/usrp2/gpif/gpif_rd.v @@ -0,0 +1,111 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module gpif_rd + (input gpif_clk, input gpif_rst, + output [15:0] gpif_data, input gpif_rd, input gpif_ep, + output reg gpif_empty_d, output reg gpif_empty_c, + output reg gpif_flush, + + input sys_clk, input sys_rst, + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, + output [31:0] debug + ); + + wire [18:0] data_o; // occ bit indicates flush + wire [17:0] resp_o; // no occ bit + wire final_rdy_data, final_rdy_resp; + + // 33/257 Bug Fix + reg [8:0] read_count; + always @(negedge gpif_clk) + if(gpif_rst) + read_count <= 0; + else if(gpif_rd) + read_count <= read_count + 1; + else + read_count <= 0; + + // Data Path + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk + (.wclk(sys_clk), .datain(data_i[18:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), + .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), + .arst(sys_rst)); + + reg [7:0] packet_count; + wire consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; + wire produce_eop = src_rdy_int & dst_rdy_int & data_int[17]; + wire consume_sop = consume_data_line & final_rdy_data & data_o[16]; + wire consume_eop = consume_data_line & final_rdy_data & data_o[17]; + + fifo_cascade #(.WIDTH(19), .SIZE(10)) rd_fifo + (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), + .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied()); + + always @(negedge gpif_clk) + if(gpif_rst) + packet_count <= 0; + else + if(produce_eop & ~consume_sop) + packet_count <= packet_count + 1; + else if(consume_sop & ~produce_eop) + packet_count <= packet_count - 1; + + always @(negedge gpif_clk) + if(gpif_rst) + gpif_empty_d <= 1; + else + gpif_empty_d <= ~|packet_count; + + // Use occ bit to signal a gpif flush + always @(negedge gpif_clk) + if(gpif_rst) + gpif_flush <= 0; + else if(consume_eop & data_o[18]) + gpif_flush <= ~gpif_flush; + + // Response Path + wire [15:0] resp_fifolevel; + wire consume_resp_line = gpif_rd & gpif_ep & ~read_count[4]; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk + (.wclk(sys_clk), .datain(resp_i[17:0]), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), + .rclk(~gpif_clk), .dataout(resp_o), + .src_rdy_o(final_rdy_resp), .dst_rdy_i(consume_resp_line), .occupied(resp_fifolevel), + .arst(sys_rst)); + + // FIXME -- handle short packets + + always @(negedge gpif_clk) + if(gpif_rst) + gpif_empty_c <= 1; + else + gpif_empty_c <= resp_fifolevel < 16; + + // Output Mux + assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0]; + + assign debug = { { 16'd0 }, + { data_int[17:16], data_o[17:16], packet_count[3:0] }, + { consume_sop, consume_eop, final_rdy_data, data_o[18], consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} }; + +endmodule // gpif_rd diff --git a/fpga/usrp2/gpif/gpif_tb.v b/fpga/usrp2/gpif/gpif_tb.v new file mode 100644 index 000000000..686284c2b --- /dev/null +++ b/fpga/usrp2/gpif/gpif_tb.v @@ -0,0 +1,142 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module gpif_tb(); + + reg sys_clk = 0; + reg sys_rst = 1; + reg gpif_clk = 0; + reg gpif_rst = 1; + + reg [15:0] gpif_data; + reg WR = 0, EP = 0; + + wire CF, DF; + + wire gpif_full_d, gpif_full_c; + wire [18:0] data_o, ctrl_o, data_splt; + wire src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt; + wire ctrl_src_rdy, ctrl_dst_rdy; + + assign ctrl_dst_rdy = 1; + + initial $dumpfile("gpif_tb.vcd"); + initial $dumpvars(0,gpif_tb); + + initial #1000 gpif_rst = 0; + initial #1000 sys_rst = 0; + always #64 gpif_clk <= ~gpif_clk; + always #47.9 sys_clk <= ~sys_clk; + + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; + + assign dst_rdy_splt = 1; + + gpif_wr gpif_write + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP), + .gpif_full_d(DF), .gpif_full_c(CF), + + .sys_clk(sys_clk), .sys_rst(sys_rst), + .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), + .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); + + packet_reframer tx_packet_reframer + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .frames_per_packet(2), + .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); + + always @(posedge sys_clk) + if(ctrl_src_rdy & ctrl_dst_rdy) + $display("CTRL: %x",ctrl_o); + + always @(posedge sys_clk) + if(src_rdy_splt & dst_rdy_splt) + begin + if(data_splt[16]) + $display("<-------- DATA SOF--------->"); + $display("DATA: %x",data_splt); + if(data_splt[17]) + $display("<-------- DATA EOF--------->"); + end + + initial + begin + #10000; + repeat (1) + begin + @(posedge gpif_clk); + + WR <= 1; + gpif_data <= 256; // Length + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data + 1; + @(posedge gpif_clk); + end + WR <= 0; + + while(DF) + @(posedge gpif_clk); + repeat (16) + @(posedge gpif_clk); + + WR <= 1; + repeat(256) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + + +/* + while(DF) + @(posedge gpif_clk); + + repeat (20) + @(posedge gpif_clk); + WR <= 1; + gpif_data <= 16'h5; + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + */ + end + end // initial begin + + initial #200000 $finish; + + +endmodule // gpif_tb diff --git a/fpga/usrp2/gpif/gpif_wr.v b/fpga/usrp2/gpif/gpif_wr.v new file mode 100644 index 000000000..89fae282e --- /dev/null +++ b/fpga/usrp2/gpif/gpif_wr.v @@ -0,0 +1,95 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module gpif_wr + (input gpif_clk, input gpif_rst, + input [15:0] gpif_data, input gpif_wr, input gpif_ep, + output reg gpif_full_d, output reg gpif_full_c, + + input sys_clk, input sys_rst, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i, + output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, + output [31:0] debug ); + + reg wr_reg, ep_reg; + reg [15:0] gpif_data_reg; + + always @(posedge gpif_clk) + begin + ep_reg <= gpif_ep; + wr_reg <= gpif_wr; + gpif_data_reg <= gpif_data; + end + + reg [9:0] write_count; + + always @(posedge gpif_clk) + if(gpif_rst) + write_count <= 0; + else if(wr_reg) + write_count <= write_count + 1; + else + write_count <= 0; + + reg sop; + wire eop = (write_count == 255); + wire eop_ctrl = (write_count == 15); + + always @(posedge gpif_clk) + sop <= gpif_wr & ~wr_reg; + + // Data Path + wire [15:0] fifo_space; + always @(posedge gpif_clk) + if(gpif_rst) + gpif_full_d <= 1; + else + gpif_full_d <= fifo_space < 256; + + wire [17:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_cascade #(.WIDTH(18), .SIZE(10)) wr_fifo + (.clk(gpif_clk), .reset(gpif_rst), .clear(0), + .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk + (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), + .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), + .arst(sys_rst)); + assign data_o[18] = 1'b0; + + // Control Path + wire [15:0] ctrl_fifo_space; + always @(posedge gpif_clk) + if(gpif_rst) + gpif_full_c <= 1; + else + gpif_full_c <= ctrl_fifo_space < 16; + + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk + (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop,gpif_data_reg}), + .src_rdy_i(ep_reg & wr_reg & ~write_count[4]), .dst_rdy_o(), .space(ctrl_fifo_space), + .rclk(sys_clk), .dataout(ctrl_o[18:0]), + .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(), + .arst(sys_rst)); + + assign debug = { 16'd0, ep_reg, wr_reg, eop, sop, (~ep_reg & wr_reg & ~write_count[8]), src_rdy_int, dst_rdy_int, write_count[8:0]}; + +endmodule // gpif_wr diff --git a/fpga/usrp2/gpif/gpif_wr_tb.v b/fpga/usrp2/gpif/gpif_wr_tb.v new file mode 100644 index 000000000..171bb96a1 --- /dev/null +++ b/fpga/usrp2/gpif/gpif_wr_tb.v @@ -0,0 +1,110 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module gpif_wr_tb(); + + reg sys_clk = 0; + reg sys_rst = 1; + reg gpif_clk = 0; + reg gpif_rst = 1; + + reg [15:0] gpif_data; + reg WR = 0, EP = 0; + + wire CF, DF; + + wire gpif_full_d, gpif_full_c; + wire [18:0] data_o, ctrl_o; + wire src_rdy, dst_rdy; + wire ctrl_src_rdy, ctrl_dst_rdy; + + assign ctrl_dst_rdy = 1; + assign dst_rdy = 1; + + initial $dumpfile("gpif_wr_tb.vcd"); + initial $dumpvars(0,gpif_wr_tb); + + initial #1000 gpif_rst = 0; + initial #1000 sys_rst = 0; + always #64 gpif_clk <= ~gpif_clk; + always #47.9 sys_clk <= ~sys_clk; + + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; + + gpif_wr gpif_write + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP), + .gpif_full_d(DF), .gpif_full_c(CF), + + .sys_clk(sys_clk), .sys_rst(sys_rst), + .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), + .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); + + packet_reframer tx_packet_reframer + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + always @(posedge sys_clk) + if(ctrl_src_rdy & ctrl_dst_rdy) + $display("CTRL: %x",ctrl_o); + + always @(posedge sys_clk) + if(src_rdy & dst_rdy) + begin + if(data_o[16]) + $display("<-------- DATA SOF--------->"); + $display("DATA: %x",data_o); + if(data_o[17]) + $display("<-------- DATA EOF--------->"); + end + + initial + begin + #10000; + repeat (1) + begin + WR <= 1; + gpif_data <= 10; // Length + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data + 1; + @(posedge gpif_clk); + end + WR <= 0; + repeat (20) + @(posedge gpif_clk); + WR <= 1; + gpif_data <= 16'h5; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + end + end // initial begin + + initial #100000 $finish; + + +endmodule // gpif_wr_tb diff --git a/fpga/usrp2/gpif/packet_reframer.v b/fpga/usrp2/gpif/packet_reframer.v new file mode 100644 index 000000000..923d499ae --- /dev/null +++ b/fpga/usrp2/gpif/packet_reframer.v @@ -0,0 +1,79 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +// Join vita packets longer than one GPIF frame, drop padding on short frames + +module packet_reframer + (input clk, input reset, input clear, + input [18:0] data_i, + input src_rdy_i, + output dst_rdy_o, + output [18:0] data_o, + output src_rdy_o, + input dst_rdy_i); + + reg [1:0] state; + reg [15:0] length; + + localparam RF_IDLE = 0; + localparam RF_PKT = 1; + localparam RF_DUMP = 2; + + always @(posedge clk) + if(reset | clear) + state <= 0; + else + if(src_rdy_i & dst_rdy_i) + case(state) + RF_IDLE : + begin + length <= {data_i[14:0],1'b0}; + state <= RF_PKT; + end + RF_PKT : + begin + if(length == 2) + if(data_i[17]) + state <= RF_IDLE; + else + state <= RF_DUMP; + else + length <= length - 1; + end + RF_DUMP : + if(data_i[17]) + state <= RF_IDLE; + default : + state<= RF_IDLE; + endcase // case (state) + + assign dst_rdy_o = dst_rdy_i; // this is a little pessimistic but ok + assign src_rdy_o = src_rdy_i & (state != RF_DUMP); + + wire occ_out = 0; + wire eof_out = (state == RF_PKT) & (length == 2); + wire sof_out = (state == RF_IDLE); + wire [15:0] data_out = data_i[15:0]; + assign data_o = {occ_out, eof_out, sof_out, data_out}; + + +endmodule // packet_reframer + + + + diff --git a/fpga/usrp2/gpif/packet_splitter.v b/fpga/usrp2/gpif/packet_splitter.v new file mode 100644 index 000000000..ba4c8cded --- /dev/null +++ b/fpga/usrp2/gpif/packet_splitter.v @@ -0,0 +1,123 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +// Split vita packets longer than one GPIF frame, add padding on short frames + +module packet_splitter + #(parameter FRAME_LEN=256) + (input clk, input reset, input clear, + input [7:0] frames_per_packet, + input [18:0] data_i, + input src_rdy_i, + output dst_rdy_o, + output [18:0] data_o, + output src_rdy_o, + input dst_rdy_i, + output [31:0] debug0, + output [31:0] debug1); + + reg [1:0] state; + reg [15:0] length; + reg [15:0] frame_len; + reg [7:0] frame_count; + + localparam PS_IDLE = 0; + localparam PS_FRAME = 1; + localparam PS_NEW_FRAME = 2; + localparam PS_PAD = 3; + + wire eof_i = data_i[17]; + + always @(posedge clk) + if(reset | clear) + begin + state <= PS_IDLE; + frame_count <= 0; + end + else + case(state) + PS_IDLE : + if(src_rdy_i & dst_rdy_i) + begin + length <= { data_i[14:0],1'b0}; + frame_len <= FRAME_LEN; + state <= PS_FRAME; + frame_count <= 1; + end + PS_FRAME : + if(src_rdy_i & dst_rdy_i) + if((frame_len == 2) & ((length == 2) | eof_i)) + state <= PS_IDLE; + else if(frame_len == 2) + begin + length <= length - 1; + state <= PS_NEW_FRAME; + frame_count <= frame_count + 1; + end + else if((length == 2)|eof_i) + begin + frame_len <= frame_len - 1; + state <= PS_PAD; + end + else + begin + frame_len <= frame_len - 1; + length <= length - 1; + end + PS_NEW_FRAME : + if(src_rdy_i & dst_rdy_i) + begin + frame_len <= FRAME_LEN; + if((length == 2)|eof_i) + state <= PS_PAD; + else + begin + state <= PS_FRAME; + length <= length - 1; + end // else: !if((length == 2)|eof_i) + end // if (src_rdy_i & dst_rdy_i) + + PS_PAD : + if(dst_rdy_i) + if(frame_len == 2) + state <= PS_IDLE; + else + frame_len <= frame_len - 1; + + endcase // case (state) + + wire next_state_is_idle = dst_rdy_i & (frame_len==2) & + ( (state==PS_PAD) | ( (state==PS_FRAME) & src_rdy_i & ((length==2)|eof_i) ) ); + + + + + assign dst_rdy_o = dst_rdy_i & (state != PS_PAD); + assign src_rdy_o = src_rdy_i | (state == PS_PAD); + + wire eof_out = (frame_len == 2) & (state != PS_IDLE) & (state != PS_NEW_FRAME); + wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME); + wire occ_out = eof_out & next_state_is_idle & (frames_per_packet != frame_count); + + wire [15:0] data_out = data_i[15:0]; + assign data_o = {occ_out, eof_out, sof_out, data_out}; + + assign debug0 = { 8'd0, dst_rdy_o, src_rdy_o, next_state_is_idle, eof_out, sof_out, occ_out, state[1:0], frame_count[7:0], frames_per_packet[7:0] }; + assign debug1 = { length[15:0], frame_len[15:0] }; + +endmodule // packet_splitter diff --git a/fpga/usrp2/gpif/packet_splitter_tb.v b/fpga/usrp2/gpif/packet_splitter_tb.v new file mode 100644 index 000000000..329b58e0d --- /dev/null +++ b/fpga/usrp2/gpif/packet_splitter_tb.v @@ -0,0 +1,137 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module packet_splitter_tb(); + + reg sys_clk = 0; + reg sys_rst = 1; + reg gpif_clk = 0; + reg gpif_rst = 1; + + reg [15:0] gpif_data; + reg WR = 0, EP = 0; + + wire CF, DF; + + wire gpif_full_d, gpif_full_c; + wire [18:0] data_o, ctrl_o, data_splt; + wire src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt; + wire ctrl_src_rdy, ctrl_dst_rdy; + + assign ctrl_dst_rdy = 1; + + initial $dumpfile("packet_splitter_tb.vcd"); + initial $dumpvars(0,packet_splitter_tb); + + initial #1000 gpif_rst = 0; + initial #1000 sys_rst = 0; + always #64 gpif_clk <= ~gpif_clk; + always #47.9 sys_clk <= ~sys_clk; + + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + + assign dst_rdy_splt = 1; + + vita_pkt_gen vita_pkt_gen + (.clk(sys_clk), .reset(sys_rst) , .clear(0), + .len(512),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), + .f19_dataout(data_o), .f19_src_rdy_o(src_rdy), .f19_dst_rdy_i(dst_rdy)); + + packet_splitter #(.FRAME_LEN(13)) rx_packet_splitter + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .frames_per_packet(4), + .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); + + always @(posedge sys_clk) + if(ctrl_src_rdy & ctrl_dst_rdy) + $display("CTRL: %x",ctrl_o); + + always @(posedge sys_clk) + if(src_rdy_splt & dst_rdy_splt) + begin + if(data_splt[16]) + $display("<-------- DATA SOF--------->"); + $display("DATA: %x",data_splt); + if(data_splt[17]) + $display("<-------- DATA EOF--------->"); + end + + initial + begin + #10000; + repeat (1) + begin + @(posedge gpif_clk); + + WR <= 1; + gpif_data <= 256; // Length + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data + 1; + @(posedge gpif_clk); + end + WR <= 0; + + while(DF) + @(posedge gpif_clk); + repeat (16) + @(posedge gpif_clk); + + WR <= 1; + repeat(256) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + + +/* + while(DF) + @(posedge gpif_clk); + + repeat (20) + @(posedge gpif_clk); + WR <= 1; + gpif_data <= 16'h5; + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + */ + end + end // initial begin + + initial #200000 $finish; + + +endmodule // packet_splitter_tb |