diff options
Diffstat (limited to 'fpga/usrp2/fifo')
| -rw-r--r-- | fpga/usrp2/fifo/packet_router.v | 18 |
1 files changed, 2 insertions, 16 deletions
diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v index 7774ff076..04c17b647 100644 --- a/fpga/usrp2/fifo/packet_router.v +++ b/fpga/usrp2/fifo/packet_router.v @@ -251,28 +251,14 @@ module packet_router //////////////////////////////////////////////////////////////////// //dummy signals to connect the components below - wire [18:0] _udp_r2s_data, _udp_s2r_data; - wire _udp_r2s_valid, _udp_s2r_valid; - wire _udp_r2s_ready, _udp_s2r_ready; - wire [35:0] _com_out_data; wire _com_out_valid, _com_out_ready; - fifo36_to_fifo19 udp_fifo36_to_fifo19 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready), - .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) ); - prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .datain(_udp_r2s_data), .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready), - .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready) ); - - fifo19_to_fifo36 udp_fifo19_to_fifo36 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready), - .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid), .f36_dst_rdy_i(_com_out_ready) ); + .datain(udp_out_data), .src_rdy_i(udp_out_valid), .dst_rdy_o(udp_out_ready), + .dataout(_com_out_data), .src_rdy_o(_com_out_valid), .dst_rdy_i(_com_out_ready) ); fifo36_mux com_out_mux( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), |