diff options
Diffstat (limited to 'fpga/usrp2/fifo')
| -rw-r--r-- | fpga/usrp2/fifo/packet_router.v | 18 | ||||
| -rw-r--r-- | fpga/usrp2/fifo/packet_verifier32.v | 23 |
2 files changed, 10 insertions, 31 deletions
diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v index 7774ff076..04c17b647 100644 --- a/fpga/usrp2/fifo/packet_router.v +++ b/fpga/usrp2/fifo/packet_router.v @@ -251,28 +251,14 @@ module packet_router //////////////////////////////////////////////////////////////////// //dummy signals to connect the components below - wire [18:0] _udp_r2s_data, _udp_s2r_data; - wire _udp_r2s_valid, _udp_s2r_valid; - wire _udp_r2s_ready, _udp_s2r_ready; - wire [35:0] _com_out_data; wire _com_out_valid, _com_out_ready; - fifo36_to_fifo19 udp_fifo36_to_fifo19 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready), - .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) ); - prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .datain(_udp_r2s_data), .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready), - .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready) ); - - fifo19_to_fifo36 udp_fifo19_to_fifo36 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready), - .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid), .f36_dst_rdy_i(_com_out_ready) ); + .datain(udp_out_data), .src_rdy_i(udp_out_valid), .dst_rdy_o(udp_out_ready), + .dataout(_com_out_data), .src_rdy_o(_com_out_valid), .dst_rdy_i(_com_out_ready) ); fifo36_mux com_out_mux( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), diff --git a/fpga/usrp2/fifo/packet_verifier32.v b/fpga/usrp2/fifo/packet_verifier32.v index 06a13d242..ec08e657d 100644 --- a/fpga/usrp2/fifo/packet_verifier32.v +++ b/fpga/usrp2/fifo/packet_verifier32.v @@ -5,26 +5,19 @@ module packet_verifier32 input [35:0] data_i, input src_rdy_i, output dst_rdy_o, output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err); - wire [7:0] ll_data; - wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; - wire [35:0] data_int; - wire src_rdy_int, dst_rdy_int; - - fifo_short #(.WIDTH(36)) fifo_short - (.clk(clk), .reset(reset), .clear(clear), - .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); - + wire [7:0] ll_data; + wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy; + fifo36_to_ll8 f36_to_ll8 (.clk(clk), .reset(reset), .clear(clear), - .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), - .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), - .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); + .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), + .ll_data(ll_data), .ll_sof(ll_sof), .ll_eof(ll_eof), + .ll_src_rdy(ll_src_rdy), .ll_dst_rdy(ll_dst_rdy)); packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear), - .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n), - .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy), + .data_i(ll_data), .sof_i(ll_sof), .eof_i(ll_eof), + .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy), .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); endmodule // packet_verifier32 |