diff options
Diffstat (limited to 'fpga/usrp2/fifo')
| -rw-r--r-- | fpga/usrp2/fifo/fifo18_to_fifo36.v | 20 | ||||
| -rw-r--r-- | fpga/usrp2/fifo/fifo36_mux.v | 19 | ||||
| -rw-r--r-- | fpga/usrp2/fifo/fifo_2clock_cascade.v | 14 |
3 files changed, 43 insertions, 10 deletions
diff --git a/fpga/usrp2/fifo/fifo18_to_fifo36.v b/fpga/usrp2/fifo/fifo18_to_fifo36.v new file mode 100644 index 000000000..25bb215a1 --- /dev/null +++ b/fpga/usrp2/fifo/fifo18_to_fifo36.v @@ -0,0 +1,20 @@ + +// For now just assume FIFO18 is same as FIFO19 without occupancy bit + +module fifo18_to_fifo36 + (input clk, input reset, input clear, + input [17:0] f18_datain, + input f18_src_rdy_i, + output f18_dst_rdy_o, + + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i + ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk), .reset(reset), .clear(clear), + .f19_datain({1'b0,f18_datain}), .f19_src_rdy_i(f18_src_rdy_i), .f19_dst_rdy_o(f18_dst_rdy_o), + .f36_dataout(f36_dataout), .f36_src_rdy_o(f36_src_rdy_o), .f36_dst_rdy_i(f36_dst_rdy_i) ); + +endmodule // fifo18_to_fifo36 diff --git a/fpga/usrp2/fifo/fifo36_mux.v b/fpga/usrp2/fifo/fifo36_mux.v index 92bf13ff9..c6fd40f27 100644 --- a/fpga/usrp2/fifo/fifo36_mux.v +++ b/fpga/usrp2/fifo/fifo36_mux.v @@ -20,6 +20,9 @@ module fifo36_mux wire eof0 = data0_i[33]; wire eof1 = data1_i[33]; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + always @(posedge clk) if(reset | clear) state <= MUX_IDLE0; @@ -32,7 +35,7 @@ module fifo36_mux state <= MUX_DATA1; MUX_DATA0 : - if(src0_rdy_i & dst_rdy_i & eof0) + if(src0_rdy_i & dst_rdy_int & eof0) state <= prio ? MUX_IDLE0 : MUX_IDLE1; MUX_IDLE1 : @@ -42,16 +45,20 @@ module fifo36_mux state <= MUX_DATA0; MUX_DATA1 : - if(src1_rdy_i & dst_rdy_i & eof1) + if(src1_rdy_i & dst_rdy_int & eof1) state <= MUX_IDLE0; default : state <= MUX_IDLE0; endcase // case (state) - assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0; - assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0; - assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_o = (state==MUX_DATA0) ? data0_i : data1_i; + assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0; + assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0; + assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; + assign data_int = (state==MUX_DATA0) ? data0_i : data1_i; + fifo_short #(.WIDTH(36)) mux_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); endmodule // fifo36_demux diff --git a/fpga/usrp2/fifo/fifo_2clock_cascade.v b/fpga/usrp2/fifo/fifo_2clock_cascade.v index 5ce726977..4e8c244c2 100644 --- a/fpga/usrp2/fifo/fifo_2clock_cascade.v +++ b/fpga/usrp2/fifo/fifo_2clock_cascade.v @@ -1,8 +1,10 @@ module fifo_2clock_cascade #(parameter WIDTH=32, SIZE=9) - (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, - input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, + output [15:0] space, output [15:0] short_space, + input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, + output [15:0] occupied, output [15:0] short_occupied, input arst); wire [WIDTH-1:0] data_int1, data_int2; @@ -29,7 +31,11 @@ module fifo_2clock_cascade .space(s2_space), .occupied(s2_occupied)); // Be conservative -- Only advertise space from input side of fifo, occupied from output side - assign space = {11'b0,s1_space} + l_space; - assign occupied = {11'b0,s2_occupied} + l_occupied; + assign space = {11'b0,s1_space} + l_space; + assign occupied = {11'b0,s2_occupied} + l_occupied; + + // For the fifo_extram, we only want to know the immediately adjacent space + assign short_space = {11'b0,s1_space}; + assign short_occupied = {11'b0,s2_occupied}; endmodule // fifo_2clock_cascade |