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-rw-r--r--fpga/usrp2/fifo/Makefile.srcs2
-rw-r--r--fpga/usrp2/fifo/fifo36_demux.v50
-rw-r--r--fpga/usrp2/fifo/fifo36_mux.v57
-rw-r--r--fpga/usrp2/fifo/fifo_new_tb.vcd5506
-rw-r--r--fpga/usrp2/fifo/fifo_tb.v25
5 files changed, 131 insertions, 5509 deletions
diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs
index 22867da7e..c66979132 100644
--- a/fpga/usrp2/fifo/Makefile.srcs
+++ b/fpga/usrp2/fifo/Makefile.srcs
@@ -20,4 +20,6 @@ fifo19_to_ll8.v \
ll8_to_fifo19.v \
fifo36_to_fifo19.v \
fifo19_to_fifo36.v \
+fifo36_mux.v \
+fifo36_demux.v \
))
diff --git a/fpga/usrp2/fifo/fifo36_demux.v b/fpga/usrp2/fifo/fifo36_demux.v
new file mode 100644
index 000000000..a54759d4d
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo36_demux.v
@@ -0,0 +1,50 @@
+
+// Demux packets from a fifo based on the contents of the first line
+// If first line matches the parameter and mask, send to data1, otherwise send to data0
+
+module fifo36_demux
+ #(parameter match_data = 0,
+ parameter match_mask = 0)
+ (input clk, input reset, input clear,
+ input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+ output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i,
+ output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i);
+
+ localparam DMX_IDLE = 0;
+ localparam DMX_DATA0 = 1;
+ localparam DMX_DATA1 = 2;
+
+ reg [1:0] state;
+
+ wire match = |( (data_i ^ match_data) & match_mask );
+ wire eof = data_i[33];
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= DMX_IDLE;
+ else
+ case(state)
+ DMX_IDLE :
+ if(src_rdy_i)
+ if(match)
+ state <= DMX_DATA1;
+ else
+ state <= DMX_DATA0;
+ DMX_DATA0 :
+ if(src_rdy_i & dst0_rdy_i & eof)
+ state <= DMX_IDLE;
+ DMX_DATA1 :
+ if(src_rdy_i & dst1_rdy_i & eof)
+ state <= DMX_IDLE;
+ default :
+ state <= DMX_IDLE;
+ endcase // case (state)
+
+ assign dst_rdy_o = (state==DMX_IDLE) ? 0 : (state==DMX_DATA0) ? dst0_rdy_i : dst1_rdy_i;
+ assign src0_rdy_o = (state==DMX_DATA0) ? src_rdy_i : 0;
+ assign src1_rdy_o = (state==DMX_DATA1) ? src_rdy_i : 0;
+
+ assign data0_o = data_i;
+ assign data1_o = data_i;
+
+endmodule // fifo36_demux
diff --git a/fpga/usrp2/fifo/fifo36_mux.v b/fpga/usrp2/fifo/fifo36_mux.v
new file mode 100644
index 000000000..92bf13ff9
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo36_mux.v
@@ -0,0 +1,57 @@
+
+// Mux packets from multiple FIFO interfaces onto a single one.
+// Can alternate or give priority to one port (port 0)
+// In prio mode, port 1 will never get access if port 0 is always busy
+
+module fifo36_mux
+ #(parameter prio = 0)
+ (input clk, input reset, input clear,
+ input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
+ input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
+ output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+ localparam MUX_IDLE0 = 0;
+ localparam MUX_DATA0 = 1;
+ localparam MUX_IDLE1 = 2;
+ localparam MUX_DATA1 = 3;
+
+ reg [1:0] state;
+
+ wire eof0 = data0_i[33];
+ wire eof1 = data1_i[33];
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= MUX_IDLE0;
+ else
+ case(state)
+ MUX_IDLE0 :
+ if(src0_rdy_i)
+ state <= MUX_DATA0;
+ else if(src1_rdy_i)
+ state <= MUX_DATA1;
+
+ MUX_DATA0 :
+ if(src0_rdy_i & dst_rdy_i & eof0)
+ state <= prio ? MUX_IDLE0 : MUX_IDLE1;
+
+ MUX_IDLE1 :
+ if(src1_rdy_i)
+ state <= MUX_DATA1;
+ else if(src0_rdy_i)
+ state <= MUX_DATA0;
+
+ MUX_DATA1 :
+ if(src1_rdy_i & dst_rdy_i & eof1)
+ state <= MUX_IDLE0;
+
+ default :
+ state <= MUX_IDLE0;
+ endcase // case (state)
+
+ assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0;
+ assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0;
+ assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
+ assign data_o = (state==MUX_DATA0) ? data0_i : data1_i;
+
+endmodule // fifo36_demux
diff --git a/fpga/usrp2/fifo/fifo_new_tb.vcd b/fpga/usrp2/fifo/fifo_new_tb.vcd
deleted file mode 100644
index 796889e7d..000000000
--- a/fpga/usrp2/fifo/fifo_new_tb.vcd
+++ /dev/null
@@ -1,5506 +0,0 @@
-$date
- Thu Mar 19 17:21:11 2009
-$end
-$version
- Icarus Verilog
-$end
-$timescale
- 1ps
-$end
-$scope module fifo_new_tb $end
-$var wire 1 ! dst_rdy_f36i $end
-$var wire 36 " f36_in [35:0] $end
-$var wire 36 # i1 [35:0] $end
-$var wire 1 $ i1_dr $end
-$var wire 1 % i1_sr $end
-$var wire 19 & i2 [18:0] $end
-$var wire 1 ' i2_dr $end
-$var wire 1 ( i2_sr $end
-$var wire 19 ) i3 [18:0] $end
-$var wire 1 * i3_dr $end
-$var wire 1 + i3_sr $end
-$var wire 36 , i4 [35:0] $end
-$var wire 1 - i4_sr $end
-$var wire 8 . ll_data [7:0] $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 2 ll_src_rdy_n $end
-$var reg 1 3 clear $end
-$var reg 1 4 clk $end
-$var reg 16 5 count [15:0] $end
-$var reg 1 6 dst_rdy_f36o $end
-$var reg 32 7 f36_data [31:0] $end
-$var reg 1 8 f36_eof $end
-$var reg 2 9 f36_occ [1:0] $end
-$var reg 1 : f36_sof $end
-$var reg 1 ; i4_dr $end
-$var reg 1 < rst $end
-$var reg 1 = src_rdy_f36i $end
-$scope module fifo_short1 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 36 @ datain [35:0] $end
-$var wire 36 A dataout [35:0] $end
-$var wire 1 $ dst_rdy_i $end
-$var wire 1 ! dst_rdy_o $end
-$var wire 1 B read $end
-$var wire 1 C reset $end
-$var wire 1 D src_rdy_i $end
-$var wire 1 % src_rdy_o $end
-$var wire 1 E write $end
-$var reg 4 F a [3:0] $end
-$var reg 1 G empty $end
-$var reg 1 H full $end
-$var reg 5 I occupied [4:0] $end
-$var reg 5 J space [4:0] $end
-$scope begin gen_srl16[0] $end
-$scope module srl16e $end
-$var wire 1 K A0 $end
-$var wire 1 L A1 $end
-$var wire 1 M A2 $end
-$var wire 1 N A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 O D $end
-$var wire 1 P Q $end
-$var reg 16 Q data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[1] $end
-$scope module srl16e $end
-$var wire 1 R A0 $end
-$var wire 1 S A1 $end
-$var wire 1 T A2 $end
-$var wire 1 U A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 V D $end
-$var wire 1 W Q $end
-$var reg 16 X data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[2] $end
-$scope module srl16e $end
-$var wire 1 Y A0 $end
-$var wire 1 Z A1 $end
-$var wire 1 [ A2 $end
-$var wire 1 \ A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 ] D $end
-$var wire 1 ^ Q $end
-$var reg 16 _ data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[3] $end
-$scope module srl16e $end
-$var wire 1 ` A0 $end
-$var wire 1 a A1 $end
-$var wire 1 b A2 $end
-$var wire 1 c A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 d D $end
-$var wire 1 e Q $end
-$var reg 16 f data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[4] $end
-$scope module srl16e $end
-$var wire 1 g A0 $end
-$var wire 1 h A1 $end
-$var wire 1 i A2 $end
-$var wire 1 j A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 k D $end
-$var wire 1 l Q $end
-$var reg 16 m data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[5] $end
-$scope module srl16e $end
-$var wire 1 n A0 $end
-$var wire 1 o A1 $end
-$var wire 1 p A2 $end
-$var wire 1 q A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 r D $end
-$var wire 1 s Q $end
-$var reg 16 t data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[6] $end
-$scope module srl16e $end
-$var wire 1 u A0 $end
-$var wire 1 v A1 $end
-$var wire 1 w A2 $end
-$var wire 1 x A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 y D $end
-$var wire 1 z Q $end
-$var reg 16 { data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[7] $end
-$scope module srl16e $end
-$var wire 1 | A0 $end
-$var wire 1 } A1 $end
-$var wire 1 ~ A2 $end
-$var wire 1 !" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 "" D $end
-$var wire 1 #" Q $end
-$var reg 16 $" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[8] $end
-$scope module srl16e $end
-$var wire 1 %" A0 $end
-$var wire 1 &" A1 $end
-$var wire 1 '" A2 $end
-$var wire 1 (" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 )" D $end
-$var wire 1 *" Q $end
-$var reg 16 +" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[9] $end
-$scope module srl16e $end
-$var wire 1 ," A0 $end
-$var wire 1 -" A1 $end
-$var wire 1 ." A2 $end
-$var wire 1 /" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 0" D $end
-$var wire 1 1" Q $end
-$var reg 16 2" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[10] $end
-$scope module srl16e $end
-$var wire 1 3" A0 $end
-$var wire 1 4" A1 $end
-$var wire 1 5" A2 $end
-$var wire 1 6" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 7" D $end
-$var wire 1 8" Q $end
-$var reg 16 9" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[11] $end
-$scope module srl16e $end
-$var wire 1 :" A0 $end
-$var wire 1 ;" A1 $end
-$var wire 1 <" A2 $end
-$var wire 1 =" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 >" D $end
-$var wire 1 ?" Q $end
-$var reg 16 @" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[12] $end
-$scope module srl16e $end
-$var wire 1 A" A0 $end
-$var wire 1 B" A1 $end
-$var wire 1 C" A2 $end
-$var wire 1 D" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 E" D $end
-$var wire 1 F" Q $end
-$var reg 16 G" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[13] $end
-$scope module srl16e $end
-$var wire 1 H" A0 $end
-$var wire 1 I" A1 $end
-$var wire 1 J" A2 $end
-$var wire 1 K" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 L" D $end
-$var wire 1 M" Q $end
-$var reg 16 N" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[14] $end
-$scope module srl16e $end
-$var wire 1 O" A0 $end
-$var wire 1 P" A1 $end
-$var wire 1 Q" A2 $end
-$var wire 1 R" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 S" D $end
-$var wire 1 T" Q $end
-$var reg 16 U" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[15] $end
-$scope module srl16e $end
-$var wire 1 V" A0 $end
-$var wire 1 W" A1 $end
-$var wire 1 X" A2 $end
-$var wire 1 Y" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 Z" D $end
-$var wire 1 [" Q $end
-$var reg 16 \" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[16] $end
-$scope module srl16e $end
-$var wire 1 ]" A0 $end
-$var wire 1 ^" A1 $end
-$var wire 1 _" A2 $end
-$var wire 1 `" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 a" D $end
-$var wire 1 b" Q $end
-$var reg 16 c" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[17] $end
-$scope module srl16e $end
-$var wire 1 d" A0 $end
-$var wire 1 e" A1 $end
-$var wire 1 f" A2 $end
-$var wire 1 g" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 h" D $end
-$var wire 1 i" Q $end
-$var reg 16 j" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[18] $end
-$scope module srl16e $end
-$var wire 1 k" A0 $end
-$var wire 1 l" A1 $end
-$var wire 1 m" A2 $end
-$var wire 1 n" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 o" D $end
-$var wire 1 p" Q $end
-$var reg 16 q" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[19] $end
-$scope module srl16e $end
-$var wire 1 r" A0 $end
-$var wire 1 s" A1 $end
-$var wire 1 t" A2 $end
-$var wire 1 u" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 v" D $end
-$var wire 1 w" Q $end
-$var reg 16 x" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[20] $end
-$scope module srl16e $end
-$var wire 1 y" A0 $end
-$var wire 1 z" A1 $end
-$var wire 1 {" A2 $end
-$var wire 1 |" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 }" D $end
-$var wire 1 ~" Q $end
-$var reg 16 !# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[21] $end
-$scope module srl16e $end
-$var wire 1 "# A0 $end
-$var wire 1 ## A1 $end
-$var wire 1 $# A2 $end
-$var wire 1 %# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 &# D $end
-$var wire 1 '# Q $end
-$var reg 16 (# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[22] $end
-$scope module srl16e $end
-$var wire 1 )# A0 $end
-$var wire 1 *# A1 $end
-$var wire 1 +# A2 $end
-$var wire 1 ,# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 -# D $end
-$var wire 1 .# Q $end
-$var reg 16 /# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[23] $end
-$scope module srl16e $end
-$var wire 1 0# A0 $end
-$var wire 1 1# A1 $end
-$var wire 1 2# A2 $end
-$var wire 1 3# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 4# D $end
-$var wire 1 5# Q $end
-$var reg 16 6# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[24] $end
-$scope module srl16e $end
-$var wire 1 7# A0 $end
-$var wire 1 8# A1 $end
-$var wire 1 9# A2 $end
-$var wire 1 :# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 ;# D $end
-$var wire 1 <# Q $end
-$var reg 16 =# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[25] $end
-$scope module srl16e $end
-$var wire 1 ># A0 $end
-$var wire 1 ?# A1 $end
-$var wire 1 @# A2 $end
-$var wire 1 A# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 B# D $end
-$var wire 1 C# Q $end
-$var reg 16 D# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[26] $end
-$scope module srl16e $end
-$var wire 1 E# A0 $end
-$var wire 1 F# A1 $end
-$var wire 1 G# A2 $end
-$var wire 1 H# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 I# D $end
-$var wire 1 J# Q $end
-$var reg 16 K# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[27] $end
-$scope module srl16e $end
-$var wire 1 L# A0 $end
-$var wire 1 M# A1 $end
-$var wire 1 N# A2 $end
-$var wire 1 O# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 P# D $end
-$var wire 1 Q# Q $end
-$var reg 16 R# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[28] $end
-$scope module srl16e $end
-$var wire 1 S# A0 $end
-$var wire 1 T# A1 $end
-$var wire 1 U# A2 $end
-$var wire 1 V# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 W# D $end
-$var wire 1 X# Q $end
-$var reg 16 Y# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[29] $end
-$scope module srl16e $end
-$var wire 1 Z# A0 $end
-$var wire 1 [# A1 $end
-$var wire 1 \# A2 $end
-$var wire 1 ]# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 ^# D $end
-$var wire 1 _# Q $end
-$var reg 16 `# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[30] $end
-$scope module srl16e $end
-$var wire 1 a# A0 $end
-$var wire 1 b# A1 $end
-$var wire 1 c# A2 $end
-$var wire 1 d# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 e# D $end
-$var wire 1 f# Q $end
-$var reg 16 g# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[31] $end
-$scope module srl16e $end
-$var wire 1 h# A0 $end
-$var wire 1 i# A1 $end
-$var wire 1 j# A2 $end
-$var wire 1 k# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 l# D $end
-$var wire 1 m# Q $end
-$var reg 16 n# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[32] $end
-$scope module srl16e $end
-$var wire 1 o# A0 $end
-$var wire 1 p# A1 $end
-$var wire 1 q# A2 $end
-$var wire 1 r# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 s# D $end
-$var wire 1 t# Q $end
-$var reg 16 u# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[33] $end
-$scope module srl16e $end
-$var wire 1 v# A0 $end
-$var wire 1 w# A1 $end
-$var wire 1 x# A2 $end
-$var wire 1 y# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 z# D $end
-$var wire 1 {# Q $end
-$var reg 16 |# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[34] $end
-$scope module srl16e $end
-$var wire 1 }# A0 $end
-$var wire 1 ~# A1 $end
-$var wire 1 !$ A2 $end
-$var wire 1 "$ A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 #$ D $end
-$var wire 1 $$ Q $end
-$var reg 16 %$ data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[35] $end
-$scope module srl16e $end
-$var wire 1 &$ A0 $end
-$var wire 1 '$ A1 $end
-$var wire 1 ($ A2 $end
-$var wire 1 )$ A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 *$ D $end
-$var wire 1 +$ Q $end
-$var reg 16 ,$ data [15:0] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module fifo36_to_fifo19 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 -$ f19_dataout [18:0] $end
-$var wire 1 ' f19_dst_rdy_i $end
-$var wire 1 ( f19_src_rdy_o $end
-$var wire 1 .$ f19_xfer $end
-$var wire 36 /$ f36_datain [35:0] $end
-$var wire 1 $ f36_dst_rdy_o $end
-$var wire 1 0$ f36_eof $end
-$var wire 1 1$ f36_occ $end
-$var wire 1 2$ f36_sof $end
-$var wire 1 % f36_src_rdy_i $end
-$var wire 1 3$ f36_xfer $end
-$var wire 1 4$ half_line $end
-$var wire 1 C reset $end
-$var reg 1 5$ phase $end
-$upscope $end
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-$var wire 1 6$ advance $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 7$ f19_data [18:0] $end
-$var wire 1 ' f19_dst_rdy_o $end
-$var wire 1 8$ f19_eof $end
-$var wire 1 9$ f19_occ $end
-$var wire 1 :$ f19_sof $end
-$var wire 1 ( f19_src_rdy_i $end
-$var wire 1 ;$ ll_dst_rdy $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 <$ ll_eof $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 =$ ll_sof $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 >$ ll_src_rdy $end
-$var wire 1 2 ll_src_rdy_n $end
-$var wire 1 C reset $end
-$var reg 8 ?$ ll_data [7:0] $end
-$var reg 1 @$ state $end
-$upscope $end
-$scope module ll8_to_fifo19 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 A$ f19_data [18:0] $end
-$var wire 1 * f19_dst_rdy_i $end
-$var wire 1 + f19_src_rdy_o $end
-$var wire 8 B$ ll_data [7:0] $end
-$var wire 1 C$ ll_dst_rdy $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 D$ ll_eof $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 E$ ll_sof $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 F$ ll_src_rdy $end
-$var wire 1 2 ll_src_rdy_n $end
-$var wire 1 C reset $end
-$var wire 1 G$ xfer_out $end
-$var reg 8 H$ dat0 [7:0] $end
-$var reg 8 I$ dat1 [7:0] $end
-$var reg 1 J$ f19_eof $end
-$var reg 1 K$ f19_occ $end
-$var reg 1 L$ f19_sof $end
-$var reg 2 M$ state [1:0] $end
-$upscope $end
-$scope module fifo19_to_fifo36 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 N$ f19_datain [18:0] $end
-$var wire 1 * f19_dst_rdy_o $end
-$var wire 1 O$ f19_eof $end
-$var wire 1 P$ f19_occ $end
-$var wire 1 Q$ f19_sof $end
-$var wire 1 + f19_src_rdy_i $end
-$var wire 36 R$ f36_dataout [35:0] $end
-$var wire 1 S$ f36_dst_rdy_i $end
-$var wire 1 - f36_src_rdy_o $end
-$var wire 1 C reset $end
-$var wire 1 T$ xfer_out $end
-$var reg 16 U$ dat0 [15:0] $end
-$var reg 16 V$ dat1 [15:0] $end
-$var reg 1 W$ f36_eof $end
-$var reg 1 X$ f36_occ $end
-$var reg 1 Y$ f36_sof $end
-$var reg 2 Z$ state [1:0] $end
-$upscope $end
-$scope task PutPacketInFIFO36 $end
-$var reg 32 [$ data_len [31:0] $end
-$var reg 32 \$ data_start [31:0] $end
-$upscope $end
-$scope task ReadFromFIFO36 $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
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diff --git a/fpga/usrp2/fifo/fifo_tb.v b/fpga/usrp2/fifo/fifo_tb.v
index f561df7fa..327da4700 100644
--- a/fpga/usrp2/fifo/fifo_tb.v
+++ b/fpga/usrp2/fifo/fifo_tb.v
@@ -24,20 +24,39 @@ module fifo_new_tb();
wire i1_sr, i1_dr;
wire i2_sr, i2_dr;
wire i3_sr, i3_dr;
+ wire i7_sr, i7_dr;
+
reg i4_dr = 0;
wire i4_sr;
- wire [35:0] i1, i4;
+ wire [35:0] i1, i4, i7;
wire [18:0] i2, i3;
wire [7:0] ll_data;
wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+ wire [35:0] err_dat;
+ wire err_src_rdy, err_dst_rdy;
+
+ reg trigger = 0;
+ initial #10000 trigger = 1;
fifo_short #(.WIDTH(36)) fifo_short1
(.clk(clk),.reset(rst),.clear(clear),
.datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
- .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+ .dataout(i7),.src_rdy_o(i7_sr),.dst_rdy_i(i7_dr) );
+ gen_context_pkt #(.PROT_ENG_FLAGS(1)) gcp
+ (.clk(clk),.reset(rst),.clear(clear),
+ .trigger(trigger), .sent(),
+ .streamid(32'hDEAD_F00D), .vita_time(64'h01234567_89ABCDEF), .message(32'hBEEF_2940),
+ .data_o(err_dat), .src_rdy_o(err_src_rdy), .dst_rdy_i(err_dst_rdy));
+
+ fifo36_mux #(.prio(0)) fifo36_mux
+ (.clk(clk), .reset(rst), .clear(clear),
+ .data0_i(i7), .src0_rdy_i(i7_sr), .dst0_rdy_o(i7_dr),
+ .data1_i(err_dat), .src1_rdy_i(err_src_rdy), .dst1_rdy_o(err_dst_rdy),
+ .data_o(i1), .src_rdy_o(i1_sr), .dst_rdy_i(i1_dr));
+
fifo36_to_fifo19 fifo36_to_fifo19
(.clk(clk),.reset(rst),.clear(clear),
.f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
@@ -59,7 +78,7 @@ module fifo_new_tb();
(.clk(clk),.reset(rst),.clear(clear),
.f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
.f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
-
+
task ReadFromFIFO36;
begin
$display("Read from FIFO36");
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 20:34:41 +0000