diff options
Diffstat (limited to 'fpga/usrp2/fifo')
| -rw-r--r-- | fpga/usrp2/fifo/dsp_framer36.v | 16 | ||||
| -rw-r--r-- | fpga/usrp2/fifo/packet_router.v | 18 |
2 files changed, 12 insertions, 22 deletions
diff --git a/fpga/usrp2/fifo/dsp_framer36.v b/fpga/usrp2/fifo/dsp_framer36.v index c2ae8f96c..58455cee1 100644 --- a/fpga/usrp2/fifo/dsp_framer36.v +++ b/fpga/usrp2/fifo/dsp_framer36.v @@ -1,9 +1,13 @@ -// Frame DSP packets with a header line to be handled by the protocol machine +// This has 3 functions: +// Correct the VITA packet length +// [optional] Frame DSP packets with an header line to be handled by the protocol machine +// Hold on to the packet until there is a complete one before allowing to leave module dsp_framer36 #(parameter BUF_SIZE = 9, - parameter PORT_SEL = 0) + parameter PORT_SEL = 0, + parameter PROT_ENG_FLAGS = 1) (input clk, input reset, input clear, input [35:0] data_i, input src_rdy_i, output dst_rdy_o, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); @@ -48,10 +52,10 @@ module dsp_framer36 always @(posedge clk) if(reset | clear) - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else if(do_xfer_out) if(dfifo_out_data[33]) // eof - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else pkt_len_out <= pkt_len_out + 1; @@ -59,8 +63,8 @@ module dsp_framer36 wire [1:0] port_sel_bits = PORT_SEL; - assign data_o = (pkt_len_out == 0) ? {4'b0001, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : - (pkt_len_out == 1) ? {4'b0000, dfifo_out_data[31:16],tfifo_data} : + assign data_o = (pkt_len_out == 0) ? {3'b000, 1'b1, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : + (pkt_len_out == 1) ? {3'b000, (PROT_ENG_FLAGS ? 1'b0: 1'b1), dfifo_out_data[31:16],tfifo_data} : {dfifo_out_data[35:33], 1'b0, dfifo_out_data[31:0] }; assign src_rdy_o = dfifo_out_src_rdy & tfifo_out_src_rdy; diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v index 7774ff076..04c17b647 100644 --- a/fpga/usrp2/fifo/packet_router.v +++ b/fpga/usrp2/fifo/packet_router.v @@ -251,28 +251,14 @@ module packet_router //////////////////////////////////////////////////////////////////// //dummy signals to connect the components below - wire [18:0] _udp_r2s_data, _udp_s2r_data; - wire _udp_r2s_valid, _udp_s2r_valid; - wire _udp_r2s_ready, _udp_s2r_ready; - wire [35:0] _com_out_data; wire _com_out_valid, _com_out_ready; - fifo36_to_fifo19 udp_fifo36_to_fifo19 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready), - .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) ); - prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .datain(_udp_r2s_data), .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready), - .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready) ); - - fifo19_to_fifo36 udp_fifo19_to_fifo36 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready), - .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid), .f36_dst_rdy_i(_com_out_ready) ); + .datain(udp_out_data), .src_rdy_i(udp_out_valid), .dst_rdy_o(udp_out_ready), + .dataout(_com_out_data), .src_rdy_o(_com_out_valid), .dst_rdy_i(_com_out_ready) ); fifo36_mux com_out_mux( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), |