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-rw-r--r--fpga/usrp2/fifo/.gitignore2
-rw-r--r--fpga/usrp2/fifo/fifo19_to_fifo36.v41
-rw-r--r--fpga/usrp2/fifo/fifo36_to_fifo18.v40
-rw-r--r--fpga/usrp2/fifo/fifo36_to_fifo19.v44
-rw-r--r--fpga/usrp2/fifo/fifo36_to_ll8.v1
5 files changed, 50 insertions, 78 deletions
diff --git a/fpga/usrp2/fifo/.gitignore b/fpga/usrp2/fifo/.gitignore
index cba7efc8e..866f1faad 100644
--- a/fpga/usrp2/fifo/.gitignore
+++ b/fpga/usrp2/fifo/.gitignore
@@ -1 +1,3 @@
+*.vcd
+*.lxt
a.out
diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v
index 5f9aeff9b..2f530109f 100644
--- a/fpga/usrp2/fifo/fifo19_to_fifo36.v
+++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v
@@ -1,26 +1,32 @@
+// Parameter LE tells us if we are little-endian.
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
+
module fifo19_to_fifo36
- (input clk, input reset, input clear,
- input [18:0] f19_datain,
- input f19_src_rdy_i,
- output f19_dst_rdy_o,
+ #(parameter LE=0)
+ (input clk, input reset, input clear,
+ input [18:0] f19_datain,
+ input f19_src_rdy_i,
+ output f19_dst_rdy_o,
- output [35:0] f36_dataout,
- output f36_src_rdy_o,
- input f36_dst_rdy_i,
- output [31:0] debug
- );
+ output [35:0] f36_dataout,
+ output f36_src_rdy_o,
+ input f36_dst_rdy_i,
+ output [31:0] debug
+ );
- reg f36_sof, f36_eof, f36_occ;
+ reg f36_sof, f36_eof;
+ reg [1:0] f36_occ;
- reg [1:0] state;
- reg [15:0] dat0, dat1;
+ reg [1:0] state;
+ reg [15:0] dat0, dat1;
- wire f19_sof = f19_datain[16];
- wire f19_eof = f19_datain[17];
- wire f19_occ = f19_datain[18];
+ wire f19_sof = f19_datain[16];
+ wire f19_eof = f19_datain[17];
+ wire f19_occ = f19_datain[18];
- wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+ wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
always @(posedge clk)
if(f19_src_rdy_i & ((state==0)|xfer_out))
@@ -68,7 +74,8 @@ module fifo19_to_fifo36
dat0 <= f19_datain;
assign f19_dst_rdy_o = xfer_out | (state != 2);
- assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1};
+ assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} :
+ {f36_occ,f36_eof,f36_sof,dat0,dat1};
assign f36_src_rdy_o = (state == 2);
assign debug = state;
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo18.v b/fpga/usrp2/fifo/fifo36_to_fifo18.v
deleted file mode 100644
index b636ab9ca..000000000
--- a/fpga/usrp2/fifo/fifo36_to_fifo18.v
+++ /dev/null
@@ -1,40 +0,0 @@
-
-module fifo36_to_fifo18
- (input clk, input reset, input clear,
- input [35:0] f36_datain,
- input f36_src_rdy_i,
- output f36_dst_rdy_o,
-
- output [17:0] f18_dataout,
- output f18_src_rdy_o,
- input f18_dst_rdy_i );
-
- wire f36_sof = f36_datain[32];
- wire f36_eof = f36_datain[33];
- wire f36_occ = f36_datain[35:34];
-
- reg phase;
-
- wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2));
-
- assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
- assign f18_dataout[16] = phase ? 0 : f36_sof;
- assign f18_dataout[17] = phase ? f36_eof : half_line;
-
- assign f18_src_rdy_o = f36_src_rdy_i;
- assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i;
-
- wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i;
- wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o;
-
- always @(posedge clk)
- if(reset)
- phase <= 0;
- else if(f36_xfer)
- phase <= 0;
- else if(f18_xfer)
- phase <= 1;
-
-
-endmodule // fifo36_to_fifo18
-
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v
index de249aaeb..517a2a476 100644
--- a/fpga/usrp2/fifo/fifo36_to_fifo19.v
+++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v
@@ -1,33 +1,38 @@
-module fifo36_to_fifo19
- (input clk, input reset, input clear,
- input [35:0] f36_datain,
- input f36_src_rdy_i,
- output f36_dst_rdy_o,
-
- output [18:0] f19_dataout,
- output f19_src_rdy_o,
- input f19_dst_rdy_i );
+// Parameter LE tells us if we are little-endian.
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
+module fifo36_to_fifo19
+ #(parameter LE=0)
+ (input clk, input reset, input clear,
+ input [35:0] f36_datain,
+ input f36_src_rdy_i,
+ output f36_dst_rdy_o,
+
+ output [18:0] f19_dataout,
+ output f19_src_rdy_o,
+ input f19_dst_rdy_i );
+
wire f36_sof = f36_datain[32];
wire f36_eof = f36_datain[33];
wire f36_occ = f36_datain[35:34];
-
- reg phase;
-
- wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2));
- assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+ reg phase;
+
+ wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2));
+
+ assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16];
assign f19_dataout[16] = phase ? 0 : f36_sof;
assign f19_dataout[17] = phase ? f36_eof : half_line;
assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
assign f19_src_rdy_o = f36_src_rdy_i;
assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i;
-
- wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i;
- wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o;
-
+
+ wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i;
+ wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o;
+
always @(posedge clk)
if(reset)
phase <= 0;
@@ -36,6 +41,5 @@ module fifo36_to_fifo19
else if(f19_xfer)
phase <= 1;
-
+
endmodule // fifo36_to_fifo19
-
diff --git a/fpga/usrp2/fifo/fifo36_to_ll8.v b/fpga/usrp2/fifo/fifo36_to_ll8.v
index 0dee1dfc6..9604d0e38 100644
--- a/fpga/usrp2/fifo/fifo36_to_ll8.v
+++ b/fpga/usrp2/fifo/fifo36_to_ll8.v
@@ -55,6 +55,5 @@ module fifo36_to_ll8
assign advance = ll_src_rdy & ll_dst_rdy;
assign f36_dst_rdy_o = advance & ((state==3)|ll_eof);
- assign debug = state;
endmodule // ll8_to_fifo36
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 15:19:04 +0000