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-rw-r--r--fpga/usrp2/fifo/.gitignore1
-rw-r--r--fpga/usrp2/fifo/Makefile.srcs23
-rw-r--r--fpga/usrp2/fifo/buffer_int.v168
-rw-r--r--fpga/usrp2/fifo/buffer_int_tb.v418
-rw-r--r--fpga/usrp2/fifo/buffer_pool.v283
-rw-r--r--fpga/usrp2/fifo/buffer_pool_tb.v58
-rw-r--r--fpga/usrp2/fifo/fifo19_to_fifo36.v76
-rw-r--r--fpga/usrp2/fifo/fifo19_to_ll8.v53
-rw-r--r--fpga/usrp2/fifo/fifo36_to_fifo18.v40
-rw-r--r--fpga/usrp2/fifo/fifo36_to_fifo19.v41
-rw-r--r--fpga/usrp2/fifo/fifo36_to_ll8.v60
-rw-r--r--fpga/usrp2/fifo/fifo_2clock.v117
-rw-r--r--fpga/usrp2/fifo/fifo_2clock_cascade.v35
-rw-r--r--fpga/usrp2/fifo/fifo_cascade.v52
-rw-r--r--fpga/usrp2/fifo/fifo_long.v148
-rw-r--r--fpga/usrp2/fifo/fifo_new_tb.vcd5506
-rw-r--r--fpga/usrp2/fifo/fifo_short.v95
-rw-r--r--fpga/usrp2/fifo/fifo_spec.txt36
-rw-r--r--fpga/usrp2/fifo/fifo_tb.v158
-rw-r--r--fpga/usrp2/fifo/ll8_shortfifo.v13
-rw-r--r--fpga/usrp2/fifo/ll8_to_fifo19.v73
-rw-r--r--fpga/usrp2/fifo/ll8_to_fifo36.v97
22 files changed, 7551 insertions, 0 deletions
diff --git a/fpga/usrp2/fifo/.gitignore b/fpga/usrp2/fifo/.gitignore
new file mode 100644
index 000000000..cba7efc8e
--- /dev/null
+++ b/fpga/usrp2/fifo/.gitignore
@@ -0,0 +1 @@
+a.out
diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs
new file mode 100644
index 000000000..22867da7e
--- /dev/null
+++ b/fpga/usrp2/fifo/Makefile.srcs
@@ -0,0 +1,23 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# FIFO Sources
+##################################################
+FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \
+buffer_int.v \
+buffer_pool.v \
+fifo_2clock.v \
+fifo_2clock_cascade.v \
+ll8_shortfifo.v \
+fifo_short.v \
+fifo_long.v \
+fifo_cascade.v \
+fifo36_to_ll8.v \
+ll8_to_fifo36.v \
+fifo19_to_ll8.v \
+ll8_to_fifo19.v \
+fifo36_to_fifo19.v \
+fifo19_to_fifo36.v \
+))
diff --git a/fpga/usrp2/fifo/buffer_int.v b/fpga/usrp2/fifo/buffer_int.v
new file mode 100644
index 000000000..b45ed3532
--- /dev/null
+++ b/fpga/usrp2/fifo/buffer_int.v
@@ -0,0 +1,168 @@
+
+// FIFO Interface to the 2K buffer RAMs
+// Read port is read-acknowledge
+// FIXME do we want to be able to interleave reads and writes?
+
+module buffer_int
+ #(parameter BUF_NUM = 0,
+ parameter BUF_SIZE = 9)
+ (// Control Interface
+ input clk,
+ input rst,
+ input [31:0] ctrl_word,
+ input go,
+ output done,
+ output error,
+ output idle,
+ output [1:0] flag,
+
+ // Buffer Interface
+ output en_o,
+ output we_o,
+ output reg [BUF_SIZE-1:0] addr_o,
+ output [31:0] dat_to_buf,
+ input [31:0] dat_from_buf,
+
+ // Write FIFO Interface
+ input [31:0] wr_data_i,
+ input [3:0] wr_flags_i,
+ input wr_ready_i,
+ output wr_ready_o,
+
+ // Read FIFO Interface
+ output [31:0] rd_data_o,
+ output [3:0] rd_flags_o,
+ output rd_ready_o,
+ input rd_ready_i
+ );
+
+ reg [31:0] ctrl_reg;
+ reg go_reg;
+
+ always @(posedge clk)
+ go_reg <= go;
+
+ always @(posedge clk)
+ if(rst)
+ ctrl_reg <= 0;
+ else
+ if(go & (ctrl_word[31:28] == BUF_NUM))
+ ctrl_reg <= ctrl_word;
+
+ wire [BUF_SIZE-1:0] firstline = ctrl_reg[BUF_SIZE-1:0];
+ wire [BUF_SIZE-1:0] lastline = ctrl_reg[2*BUF_SIZE-1:BUF_SIZE];
+
+ wire read = ctrl_reg[22];
+ wire write = ctrl_reg[23];
+ wire clear = ctrl_reg[24];
+ //wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block
+ //wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ?
+
+ localparam IDLE = 3'd0;
+ localparam PRE_READ = 3'd1;
+ localparam READING = 3'd2;
+ localparam WRITING = 3'd3;
+ localparam ERROR = 3'd4;
+ localparam DONE = 3'd5;
+
+ reg [2:0] state;
+ reg rd_sop, rd_eop;
+ wire wr_sop, wr_eop, wr_error;
+ reg [1:0] rd_occ;
+ wire [1:0] wr_occ;
+
+ always @(posedge clk)
+ if(rst)
+ begin
+ state <= IDLE;
+ rd_sop <= 0;
+ rd_eop <= 0;
+ rd_occ <= 0;
+ end
+ else
+ if(clear)
+ begin
+ state <= IDLE;
+ rd_sop <= 0;
+ rd_eop <= 0;
+ rd_occ <= 0;
+ end
+ else
+ case(state)
+ IDLE :
+ if(go_reg & read)
+ begin
+ addr_o <= firstline;
+ state <= PRE_READ;
+ end
+ else if(go_reg & write)
+ begin
+ addr_o <= firstline;
+ state <= WRITING;
+ end
+
+ PRE_READ :
+ begin
+ state <= READING;
+ addr_o <= addr_o + 1;
+ rd_occ <= 2'b00;
+ rd_sop <= 1;
+ rd_eop <= 0;
+ end
+
+ READING :
+ if(rd_ready_i)
+ begin
+ rd_sop <= 0;
+ addr_o <= addr_o + 1;
+ if(addr_o == lastline)
+ begin
+ rd_eop <= 1;
+ // FIXME assign occ here
+ rd_occ <= 0;
+ end
+ else
+ rd_eop <= 0;
+ if(rd_eop)
+ state <= DONE;
+ end
+
+ WRITING :
+ begin
+ if(wr_ready_i)
+ begin
+ addr_o <= addr_o + 1;
+ if(wr_error)
+ begin
+ state <= ERROR;
+ // Save OCC flags here
+ end
+ else if((addr_o == lastline)||wr_eop)
+ state <= DONE;
+ end // if (wr_ready_i)
+ end // case: WRITING
+
+ endcase // case(state)
+
+ assign dat_to_buf = wr_data_i;
+ assign rd_data_o = dat_from_buf;
+
+ assign rd_flags_o = { rd_occ[1:0], rd_eop, rd_sop };
+ assign rd_ready_o = (state == READING);
+
+ assign wr_sop = wr_flags_i[0];
+ assign wr_eop = wr_flags_i[1];
+ assign wr_occ = wr_flags_i[3:2];
+ assign wr_error = wr_sop & wr_eop;
+ assign wr_ready_o = (state == WRITING);
+
+ assign we_o = (state == WRITING);
+ //assign we_o = (state == WRITING) && wr_ready_i; // always write to avoid timing issue
+
+ assign en_o = ~((state==READING)& ~rd_ready_i); // FIXME potential critical path
+
+ assign done = (state == DONE);
+ assign error = (state == ERROR);
+ assign idle = (state == IDLE);
+
+endmodule // buffer_int
diff --git a/fpga/usrp2/fifo/buffer_int_tb.v b/fpga/usrp2/fifo/buffer_int_tb.v
new file mode 100644
index 000000000..df54dcc0b
--- /dev/null
+++ b/fpga/usrp2/fifo/buffer_int_tb.v
@@ -0,0 +1,418 @@
+
+module buffer_int_tb ();
+
+ reg clk = 0;
+ reg rst = 1;
+
+ initial #100 rst = 0;
+ always #5 clk = ~clk;
+
+ wire en, we;
+ wire [8:0] addr;
+ wire [31:0] fifo2buf, buf2fifo;
+
+ wire [31:0] rd_data_o;
+ wire [3:0] rd_flags_o;
+ wire rd_sop_o, rd_eop_o;
+ reg rd_error_i = 0, rd_read_i = 0;
+
+ reg [31:0] wr_data_i = 0;
+ wire [3:0] wr_flags_i;
+ reg wr_eop_i = 0, wr_sop_i = 0;
+ reg wr_write_i = 0;
+ wire wr_ready_o, wr_full_o;
+
+ reg clear = 0, write = 0, read = 0;
+ reg [8:0] firstline = 0, lastline = 0;
+ wire [3:0] step = 1;
+ wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline};
+ reg go = 0;
+ wire done, error;
+
+ assign wr_flags_i = {2'b00, wr_eop_i, wr_sop_i};
+ assign rd_sop_o = rd_flags_o[0];
+ assign rd_eop_o = rd_flags_o[1];
+
+ buffer_int buffer_int
+ (.clk(clk),.rst(rst),
+ .ctrl_word(ctrl_word),.go(go),
+ .done(done),.error(error),
+
+ // Buffer Interface
+ .en_o(en),.we_o(we),.addr_o(addr),
+ .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
+
+ // Write FIFO Interface
+ .wr_data_i(wr_data_i), .wr_flags_i(wr_flags_i), .wr_write_i(wr_write_i), .wr_ready_o(wr_ready_o),
+
+ // Read FIFO Interface
+ .rd_data_o(rd_data_o), .rd_flags_o(rd_flags_o), .rd_ready_o(rd_ready_o), .rd_read_i(rd_read_i)
+ );
+
+ reg ram_en = 0, ram_we = 0;
+ reg [8:0] ram_addr = 0;
+ reg [31:0] ram_data = 0;
+
+ ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port
+ (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(),
+ .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) );
+
+ initial
+ begin
+ @(negedge rst);
+ @(posedge clk);
+ FillRAM;
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing full read, no wait states.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(6,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing full read, 2 wait states.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(6,2);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 0 wait states, then nothing after last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(3,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 0 wait states, then done at same time as last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(2,0);
+ ReadALine;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 3 wait states, then error at same time as last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(2,3);
+ rd_error_i <= 1;
+ ReadALine;
+ rd_error_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(500,511);
+ $display("Testing full read, to the end of the buffer.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(12,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(0,511);
+ $display("Testing full read, start to end of the buffer.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(512,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(505,3);
+ $display("Testing full read, wraparound");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(11,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(10,15);
+ $display("Testing Full Write, no wait states");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,72);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(18,23);
+ $display("Testing Full Write, 1 wait states");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,1,101);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(27,40);
+ $display("Testing Partial Write, 0 wait states");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,201);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(45,200);
+ $display("Testing Partial Write, 0 wait states, then done and write simultaneously");
+ while(!wr_ready_o)
+ @(posedge clk);
+ wr_sop_i <= 1; wr_eop_i <= 0;
+ WriteLines(6,0,301);
+ wr_sop_i <= 0; wr_eop_i <= 1;
+ WriteALine(400);
+ wr_sop_i <= 0; wr_eop_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(55,200);
+ $display("Testing Partial Write, 0 wait states, then error");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,501);
+ wr_sop_i <= 1; wr_eop_i <= 1;
+ WriteALine(400);
+ @(posedge clk);
+ repeat (10)
+ @(posedge clk);
+ wr_sop_i <= 0; wr_eop_i <= 0;
+
+ ResetBuffer;
+ SetBufferRead(0,82);
+ $display("Testing read after all the writes");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(83,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(508,4);
+ $display("Testing wraparound write");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(9,0,601);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(506,10);
+ $display("Reading wraparound write");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(17,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(0,511);
+ $display("Testing Whole Buffer write");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(512,0,1000);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(0,511);
+ $display("Reading Whole Buffer write");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(512,0);
+ repeat (10)
+ @(posedge clk);
+
+ /*
+ ResetBuffer;
+ SetBufferWrite(5,10);
+ $display("Testing Write Too Many");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(12,0,2000);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(0,15);
+ $display("Reading back Write Too Many");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(16,0);
+ repeat (10)
+ @(posedge clk);
+ */
+ ResetBuffer;
+ SetBufferWrite(15,20);
+ $display("Testing Write One Less Than Full");
+ while(!wr_ready_o)
+ @(posedge clk);
+ wr_sop_i <= 1; wr_eop_i <= 0;
+ WriteALine(400);
+ wr_sop_i <= 0; wr_eop_i <= 0;
+ WriteLines(3,0,2000);
+ wr_sop_i <= 0; wr_eop_i <= 1;
+ WriteALine(400);
+ wr_sop_i <= 0; wr_eop_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(13,22);
+ $display("Reading back Write One Less Than Full");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(10,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ repeat(100)
+ @(posedge clk);
+ $finish;
+ end
+
+ always @(posedge clk)
+ if(rd_read_i == 1'd1)
+ $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_data_o, rd_sop_o, rd_eop_o);
+
+ always @(posedge clk)
+ if(wr_write_i == 1'd1)
+ $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_data_i, wr_ready_o, wr_full_o);
+
+ initial begin
+ $dumpfile("buffer_int_tb.lxt");
+ $dumpvars(0,buffer_int_tb);
+ end
+
+ task FillRAM;
+ begin
+ ram_addr <= 0;
+ ram_data <= 0;
+ @(posedge clk);
+ ram_en <= 1;
+ ram_we <= 1;
+ @(posedge clk);
+ repeat (511)
+ begin
+ ram_addr <= ram_addr + 1;
+ ram_data <= ram_data + 1;
+ ram_en <= 1;
+ ram_we <= 1;
+ @(posedge clk);
+ end
+ ram_en <= 0;
+ ram_we <= 0;
+ @(posedge clk);
+ $display("Filled the RAM");
+ end
+ endtask // FillRAM
+
+ task ResetBuffer;
+ begin
+ clear <= 1; read <= 0; write <= 0;
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ @(posedge clk);
+ $display("Buffer Reset");
+ end
+ endtask // ClearBuffer
+
+ task SetBufferWrite;
+ input [8:0] start;
+ input [8:0] stop;
+ begin
+ clear <= 0; read <= 0; write <= 1;
+ firstline <= start;
+ lastline <= stop;
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ @(posedge clk);
+ $display("Buffer Set for Write");
+ end
+ endtask // SetBufferWrite
+
+ task SetBufferRead;
+ input [8:0] start;
+ input [8:0] stop;
+ begin
+ clear <= 0; read <= 1; write <= 0;
+ firstline <= start;
+ lastline <= stop;
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ @(posedge clk);
+ $display("Buffer Set for Read");
+ end
+ endtask // SetBufferRead
+
+ task ReadALine;
+ begin
+ while(~rd_ready_o)
+ @(posedge clk);
+ #1 rd_read_i <= 1;
+ @(posedge clk);
+ rd_read_i <= 0;
+ end
+ endtask // ReadALine
+
+ task ReadLines;
+ input [9:0] lines;
+ input [7:0] wait_states;
+ begin
+ $display("Read Lines: Number %d, Wait States %d",lines,wait_states);
+ repeat (lines)
+ begin
+ ReadALine;
+ repeat (wait_states)
+ @(posedge clk);
+ end
+ end
+ endtask // ReadLines
+
+ task WriteALine;
+ input [31:0] value;
+ begin
+ while(~wr_ready_o)
+ @(posedge clk);
+ #1 wr_write_i <= 1;
+ wr_data_i <= value;
+ @(posedge clk);
+ wr_write_i <= 0;
+ end
+ endtask // WriteALine
+
+ task WriteLines;
+ input [9:0] lines;
+ input [7:0] wait_states;
+ input [31:0] value;
+ begin
+ $display("Write Lines: Number %d, Wait States %d",lines,wait_states);
+ repeat(lines)
+ begin
+ value <= value + 1;
+ WriteALine(value);
+ repeat(wait_states)
+ @(posedge clk);
+ end
+ end
+ endtask // WriteLines
+
+endmodule // buffer_int_tb
diff --git a/fpga/usrp2/fifo/buffer_pool.v b/fpga/usrp2/fifo/buffer_pool.v
new file mode 100644
index 000000000..41ac1deb3
--- /dev/null
+++ b/fpga/usrp2/fifo/buffer_pool.v
@@ -0,0 +1,283 @@
+
+// Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer
+// is a dual-ported RAM. Port A on each of them is indirectly connected
+// to the wishbone bus by a bridge. Port B may be connected any one of the
+// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected. The wishbone bus
+// provides access to all 8 buffers, and also controls the connections
+// between the ports and the buffers, allocating them as needed.
+
+// wb_adr is 16 bits --
+// bits 13:11 select which buffer
+// bits 10:2 select line in buffer
+// bits 1:0 are unused (32-bit access only)
+
+// BUF_SIZE is in address lines (i.e. log2 of number of lines).
+// For S3 it should be 9 (512 words, 2KB)
+// For V5 it should be at least 10 (1024 words, 4KB) or 11 (2048 words, 8KB)
+
+module buffer_pool
+ #(parameter BUF_SIZE = 9,
+ parameter SET_ADDR = 64)
+ (input wb_clk_i,
+ input wb_rst_i,
+ input wb_we_i,
+ input wb_stb_i,
+ input [15:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ output [31:0] wb_dat_o,
+ output reg wb_ack_o,
+ output wb_err_o,
+ output wb_rty_o,
+
+ input stream_clk,
+ input stream_rst,
+
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ output [31:0] status,
+ output sys_int_o,
+
+ output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3,
+ output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7,
+
+ // Write Interfaces
+ input [31:0] wr0_data_i, input [3:0] wr0_flags_i, input wr0_ready_i, output wr0_ready_o,
+ input [31:0] wr1_data_i, input [3:0] wr1_flags_i, input wr1_ready_i, output wr1_ready_o,
+ input [31:0] wr2_data_i, input [3:0] wr2_flags_i, input wr2_ready_i, output wr2_ready_o,
+ input [31:0] wr3_data_i, input [3:0] wr3_flags_i, input wr3_ready_i, output wr3_ready_o,
+
+ // Read Interfaces
+ output [31:0] rd0_data_o, output [3:0] rd0_flags_o, output rd0_ready_o, input rd0_ready_i,
+ output [31:0] rd1_data_o, output [3:0] rd1_flags_o, output rd1_ready_o, input rd1_ready_i,
+ output [31:0] rd2_data_o, output [3:0] rd2_flags_o, output rd2_ready_o, input rd2_ready_i,
+ output [31:0] rd3_data_o, output [3:0] rd3_flags_o, output rd3_ready_o, input rd3_ready_i
+ );
+
+ wire [7:0] sel_a;
+
+ wire [BUF_SIZE-1:0] buf_addra = wb_adr_i[BUF_SIZE+1:2]; // ignore address 1:0, 32-bit access only
+ wire [2:0] which_buf = wb_adr_i[BUF_SIZE+4:BUF_SIZE+2]; // address 15:14 selects the buffer pool
+
+ decoder_3_8 dec(.sel(which_buf),.res(sel_a));
+
+ genvar i;
+
+ wire go;
+
+ reg [2:0] port[0:7];
+ reg [3:0] read_src[0:3];
+ reg [3:0] write_src[0:3];
+
+ wire [7:0] done;
+ wire [7:0] error;
+ wire [7:0] idle;
+
+ wire [31:0] buf_doa[0:7];
+
+ wire [7:0] buf_enb;
+ wire [7:0] buf_web;
+ wire [BUF_SIZE-1:0] buf_addrb[0:7];
+ wire [31:0] buf_dib[0:7];
+ wire [31:0] buf_dob[0:7];
+
+ wire [31:0] wr_data_i[0:7];
+ wire [3:0] wr_flags_i[0:7];
+ wire [7:0] wr_ready_i;
+ wire [7:0] wr_ready_o;
+
+ wire [31:0] rd_data_o[0:7];
+ wire [3:0] rd_flags_o[0:7];
+ wire [7:0] rd_ready_o;
+ wire [7:0] rd_ready_i;
+
+ assign status = {8'd0,idle[7:0],error[7:0],done[7:0]};
+
+ assign s0 = buf_addrb[0];
+ assign s1 = buf_addrb[1];
+ assign s2 = buf_addrb[2];
+ assign s3 = buf_addrb[3];
+ assign s4 = buf_addrb[4];
+ assign s5 = buf_addrb[5];
+ assign s6 = buf_addrb[6];
+ assign s7 = buf_addrb[7];
+
+ wire [31:0] fifo_ctrl;
+ setting_reg #(.my_addr(SET_ADDR))
+ sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(fifo_ctrl),.changed(go));
+
+ integer k;
+ always @(posedge stream_clk)
+ if(stream_rst)
+ for(k=0;k<8;k=k+1)
+ port[k] <= 4; // disabled
+ else
+ for(k=0;k<8;k=k+1)
+ if(go & (fifo_ctrl[31:28]==k))
+ port[k] <= fifo_ctrl[27:25];
+
+ always @(posedge stream_clk)
+ if(stream_rst)
+ for(k=0;k<4;k=k+1)
+ read_src[k] <= 8; // disabled
+ else
+ for(k=0;k<4;k=k+1)
+ if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k))
+ read_src[k] <= fifo_ctrl[31:28];
+
+ always @(posedge stream_clk)
+ if(stream_rst)
+ for(k=0;k<4;k=k+1)
+ write_src[k] <= 8; // disabled
+ else
+ for(k=0;k<4;k=k+1)
+ if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k))
+ write_src[k] <= fifo_ctrl[31:28];
+
+ generate
+ for(i=0;i<8;i=i+1)
+ begin : gen_buffer
+ RAMB16_S36_S36 dpram
+ (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
+ .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i),
+ .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0),
+ .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) );
+
+/*
+ ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer
+ (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
+ .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
+ .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),
+ .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i]));
+
+ */
+
+ buffer_int #(.BUF_NUM(i),.BUF_SIZE(BUF_SIZE)) buffer_int
+ (.clk(stream_clk),.rst(stream_rst),
+ .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)),
+ .done(done[i]),.error(error[i]),.idle(idle[i]),
+ .en_o(buf_enb[i]),
+ .we_o(buf_web[i]),
+ .addr_o(buf_addrb[i]),
+ .dat_to_buf(buf_dib[i]),
+ .dat_from_buf(buf_dob[i]),
+ .wr_data_i(wr_data_i[i]),
+ .wr_flags_i(wr_flags_i[i]),
+ .wr_ready_i(wr_ready_i[i]),
+ .wr_ready_o(wr_ready_o[i]),
+ .rd_data_o(rd_data_o[i]),
+ .rd_flags_o(rd_flags_o[i]),
+ .rd_ready_o(rd_ready_o[i]),
+ .rd_ready_i(rd_ready_i[i]) );
+ mux4 #(.WIDTH(37))
+ mux4_wr (.en(~port[i][2]),.sel(port[i][1:0]),
+ .i0({wr0_data_i,wr0_flags_i,wr0_ready_i}),
+ .i1({wr1_data_i,wr1_flags_i,wr1_ready_i}),
+ .i2({wr2_data_i,wr2_flags_i,wr2_ready_i}),
+ .i3({wr3_data_i,wr3_flags_i,wr3_ready_i}),
+ .o({wr_data_i[i],wr_flags_i[i],wr_ready_i[i]}) );
+ mux4 #(.WIDTH(1))
+ mux4_rd (.en(~port[i][2]),.sel(port[i][1:0]),
+ .i0(rd0_ready_i),.i1(rd1_ready_i),.i2(rd2_ready_i),.i3(rd3_ready_i),
+ .o(rd_ready_i[i]));
+ end // block: gen_buffer
+ endgenerate
+
+ //----------------------------------------------------------------------
+ // Wishbone Outputs
+
+ // Use the following lines if ram output and mux can be made fast enough
+
+ assign wb_err_o = 1'b0; // Unused for now
+ assign wb_rty_o = 1'b0; // Unused for now
+
+ always @(posedge wb_clk_i)
+ wb_ack_o <= wb_stb_i & ~wb_ack_o;
+ assign wb_dat_o = buf_doa[which_buf];
+
+ // Use this if we can't make the RAM+MUX fast enough
+ // reg [31:0] wb_dat_o_reg;
+ // reg stb_d1;
+
+ // always @(posedge wb_clk_i)
+ // begin
+ // wb_dat_o_reg <= buf_doa[which_buf];
+ // stb_d1 <= wb_stb_i;
+ // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i);
+ // end
+ //assign wb_dat_o = wb_dat_o_reg;
+
+ mux8 #(.WIDTH(1))
+ mux8_wr0(.en(~write_src[0][3]),.sel(write_src[0][2:0]),
+ .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]),
+ .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),
+ .o(wr0_ready_o));
+
+ mux8 #(.WIDTH(1))
+ mux8_wr1(.en(~write_src[1][3]),.sel(write_src[1][2:0]),
+ .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]),
+ .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),
+ .o(wr1_ready_o));
+
+ mux8 #(.WIDTH(1))
+ mux8_wr2(.en(~write_src[2][3]),.sel(write_src[2][2:0]),
+ .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]),
+ .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),
+ .o(wr2_ready_o));
+
+ mux8 #(.WIDTH(1))
+ mux8_wr3(.en(~write_src[3][3]),.sel(write_src[3][2:0]),
+ .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]),
+ .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),
+ .o(wr3_ready_o));
+
+ mux8 #(.WIDTH(37))
+ mux8_rd0(.en(~read_src[0][3]),.sel(read_src[0][2:0]),
+ .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+ .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+ .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+ .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+ .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+ .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+ .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+ .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+ .o({rd0_data_o,rd0_flags_o,rd0_ready_o}));
+
+ mux8 #(.WIDTH(37))
+ mux8_rd1(.en(~read_src[1][3]),.sel(read_src[1][2:0]),
+ .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+ .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+ .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+ .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+ .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+ .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+ .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+ .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+ .o({rd1_data_o,rd1_flags_o,rd1_ready_o}));
+
+ mux8 #(.WIDTH(37))
+ mux8_rd2(.en(~read_src[2][3]),.sel(read_src[2][2:0]),
+ .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+ .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+ .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+ .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+ .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+ .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+ .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+ .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+ .o({rd2_data_o,rd2_flags_o,rd2_ready_o}));
+
+ mux8 #(.WIDTH(37))
+ mux8_rd3(.en(~read_src[3][3]),.sel(read_src[3][2:0]),
+ .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+ .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+ .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+ .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+ .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+ .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+ .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+ .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+ .o({rd3_data_o,rd3_flags_o,rd3_ready_o}));
+
+ assign sys_int_o = (|error) | (|done);
+
+endmodule // buffer_pool
diff --git a/fpga/usrp2/fifo/buffer_pool_tb.v b/fpga/usrp2/fifo/buffer_pool_tb.v
new file mode 100644
index 000000000..91a01d268
--- /dev/null
+++ b/fpga/usrp2/fifo/buffer_pool_tb.v
@@ -0,0 +1,58 @@
+
+module buffer_pool_tb();
+
+ wire wb_clk_i;
+ wire wb_rst_i;
+ wire wb_we_i;
+ wire wb_stb_i;
+ wire [15:0] wb_adr_i;
+ wire [31:0] wb_dat_i;
+ wire [31:0] wb_dat_o;
+ wire wb_ack_o;
+ wire wb_err_o;
+ wire wb_rty_o;
+
+ wire stream_clk, stream_rst;
+
+ wire set_stb;
+ wire [7:0] set_addr;
+ wire [31:0] set_data;
+
+ wire [31:0] wr0_data, wr1_data, wr2_data, wr3_data;
+ wire [31:0] rd0_data, rd1_data, rd2_data, rd3_data;
+ wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags;
+ wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags;
+ wire wr0_ready, wr1_ready, wr2_ready, wr3_ready;
+ wire rd0_ready, rd1_ready, rd2_ready, rd3_ready;
+ wire wr0_write, wr1_write, wr2_write, wr3_write;
+ wire rd0_read, rd1_read, rd2_read, rd3_read;
+
+ buffer_pool dut
+ (.wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_we_i(wb_we_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(wb_dat_o),
+ .wb_ack_o(wb_ack_o),
+ .wb_err_o(wb_err_o),
+ .wb_rty_o(wb_rty_o),
+
+ .stream_clk(stream_clk),
+ .stream_rst(stream_rst),
+
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+
+ .wr0_data_i(wr0_data), .wr0_write_i(wr0_write), .wr0_flags_i(wr0_flags), .wr0_ready_o(wr0_ready),
+ .wr1_data_i(wr1_data), .wr1_write_i(wr1_write), .wr1_flags_i(wr1_flags), .wr1_ready_o(wr1_ready),
+ .wr2_data_i(wr2_data), .wr2_write_i(wr2_write), .wr2_flags_i(wr2_flags), .wr2_ready_o(wr2_ready),
+ .wr3_data_i(wr3_data), .wr3_write_i(wr3_write), .wr3_flags_i(wr3_flags), .wr3_ready_o(wr3_ready),
+
+ .rd0_data_o(rd0_data), .rd0_read_i(rd0_read), .rd0_flags_o(rd0_flags), .rd0_ready_o(rd0_ready),
+ .rd1_data_o(rd1_data), .rd1_read_i(rd1_read), .rd1_flags_o(rd1_flags), .rd1_ready_o(rd1_ready),
+ .rd2_data_o(rd2_data), .rd2_read_i(rd2_read), .rd2_flags_o(rd2_flags), .rd2_ready_o(rd2_ready),
+ .rd3_data_o(rd3_data), .rd3_read_i(rd3_read), .rd3_flags_o(rd3_flags), .rd3_ready_o(rd3_ready)
+ );
+
+endmodule // buffer_pool_tb
diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v
new file mode 100644
index 000000000..5f9aeff9b
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v
@@ -0,0 +1,76 @@
+
+module fifo19_to_fifo36
+ (input clk, input reset, input clear,
+ input [18:0] f19_datain,
+ input f19_src_rdy_i,
+ output f19_dst_rdy_o,
+
+ output [35:0] f36_dataout,
+ output f36_src_rdy_o,
+ input f36_dst_rdy_i,
+ output [31:0] debug
+ );
+
+ reg f36_sof, f36_eof, f36_occ;
+
+ reg [1:0] state;
+ reg [15:0] dat0, dat1;
+
+ wire f19_sof = f19_datain[16];
+ wire f19_eof = f19_datain[17];
+ wire f19_occ = f19_datain[18];
+
+ wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+
+ always @(posedge clk)
+ if(f19_src_rdy_i & ((state==0)|xfer_out))
+ f36_sof <= f19_sof;
+
+ always @(posedge clk)
+ if(f19_src_rdy_i & ((state != 2)|xfer_out))
+ f36_eof <= f19_eof;
+
+ always @(posedge clk) // FIXME check this
+ if(f19_eof)
+ f36_occ <= {state[0],f19_occ};
+ else
+ f36_occ <= 0;
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(f19_src_rdy_i)
+ case(state)
+ 0 :
+ if(f19_eof)
+ state <= 2;
+ else
+ state <= 1;
+ 1 :
+ state <= 2;
+ 2 :
+ if(xfer_out)
+ if(~f19_eof)
+ state <= 1;
+ // remain in state 2 if we are at eof
+ endcase // case(state)
+ else
+ if(xfer_out)
+ state <= 0;
+
+ always @(posedge clk)
+ if(f19_src_rdy_i & (state==1))
+ dat1 <= f19_datain;
+
+ always @(posedge clk)
+ if(f19_src_rdy_i & ((state==0) | xfer_out))
+ dat0 <= f19_datain;
+
+ assign f19_dst_rdy_o = xfer_out | (state != 2);
+ assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1};
+ assign f36_src_rdy_o = (state == 2);
+
+ assign debug = state;
+
+endmodule // fifo19_to_fifo36
diff --git a/fpga/usrp2/fifo/fifo19_to_ll8.v b/fpga/usrp2/fifo/fifo19_to_ll8.v
new file mode 100644
index 000000000..4707f7523
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo19_to_ll8.v
@@ -0,0 +1,53 @@
+
+module fifo19_to_ll8
+ (input clk, input reset, input clear,
+ input [18:0] f19_data,
+ input f19_src_rdy_i,
+ output f19_dst_rdy_o,
+
+ output reg [7:0] ll_data,
+ output ll_sof_n,
+ output ll_eof_n,
+ output ll_src_rdy_n,
+ input ll_dst_rdy_n);
+
+ wire ll_sof, ll_eof, ll_src_rdy;
+ assign ll_sof_n = ~ll_sof;
+ assign ll_eof_n = ~ll_eof;
+ assign ll_src_rdy_n = ~ll_src_rdy;
+ wire ll_dst_rdy = ~ll_dst_rdy_n;
+
+ wire f19_sof = f19_data[16];
+ wire f19_eof = f19_data[17];
+ wire f19_occ = f19_data[18];
+
+ wire advance, end_early;
+ reg state;
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(advance)
+ if(ll_eof)
+ state <= 0;
+ else
+ state <= state + 1;
+
+ always @*
+ case(state)
+ 0 : ll_data = f19_data[15:8];
+ 1 : ll_data = f19_data[7:0];
+ default : ll_data = f19_data[15:8];
+ endcase // case (state)
+
+ assign ll_sof = (state==0) & f19_sof;
+ assign ll_eof = f19_eof & ((f19_occ==1)|(state==1));
+
+ assign ll_src_rdy = f19_src_rdy_i;
+
+ assign advance = ll_src_rdy & ll_dst_rdy;
+ assign f19_dst_rdy_o = advance & ((state==1)|ll_eof);
+
+endmodule // fifo19_to_ll8
+
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo18.v b/fpga/usrp2/fifo/fifo36_to_fifo18.v
new file mode 100644
index 000000000..b636ab9ca
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo36_to_fifo18.v
@@ -0,0 +1,40 @@
+
+module fifo36_to_fifo18
+ (input clk, input reset, input clear,
+ input [35:0] f36_datain,
+ input f36_src_rdy_i,
+ output f36_dst_rdy_o,
+
+ output [17:0] f18_dataout,
+ output f18_src_rdy_o,
+ input f18_dst_rdy_i );
+
+ wire f36_sof = f36_datain[32];
+ wire f36_eof = f36_datain[33];
+ wire f36_occ = f36_datain[35:34];
+
+ reg phase;
+
+ wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2));
+
+ assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+ assign f18_dataout[16] = phase ? 0 : f36_sof;
+ assign f18_dataout[17] = phase ? f36_eof : half_line;
+
+ assign f18_src_rdy_o = f36_src_rdy_i;
+ assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i;
+
+ wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i;
+ wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o;
+
+ always @(posedge clk)
+ if(reset)
+ phase <= 0;
+ else if(f36_xfer)
+ phase <= 0;
+ else if(f18_xfer)
+ phase <= 1;
+
+
+endmodule // fifo36_to_fifo18
+
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v
new file mode 100644
index 000000000..de249aaeb
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v
@@ -0,0 +1,41 @@
+
+module fifo36_to_fifo19
+ (input clk, input reset, input clear,
+ input [35:0] f36_datain,
+ input f36_src_rdy_i,
+ output f36_dst_rdy_o,
+
+ output [18:0] f19_dataout,
+ output f19_src_rdy_o,
+ input f19_dst_rdy_i );
+
+ wire f36_sof = f36_datain[32];
+ wire f36_eof = f36_datain[33];
+ wire f36_occ = f36_datain[35:34];
+
+ reg phase;
+
+ wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2));
+
+ assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+ assign f19_dataout[16] = phase ? 0 : f36_sof;
+ assign f19_dataout[17] = phase ? f36_eof : half_line;
+ assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
+
+ assign f19_src_rdy_o = f36_src_rdy_i;
+ assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i;
+
+ wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i;
+ wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o;
+
+ always @(posedge clk)
+ if(reset)
+ phase <= 0;
+ else if(f36_xfer)
+ phase <= 0;
+ else if(f19_xfer)
+ phase <= 1;
+
+
+endmodule // fifo36_to_fifo19
+
diff --git a/fpga/usrp2/fifo/fifo36_to_ll8.v b/fpga/usrp2/fifo/fifo36_to_ll8.v
new file mode 100644
index 000000000..0dee1dfc6
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo36_to_ll8.v
@@ -0,0 +1,60 @@
+
+module fifo36_to_ll8
+ (input clk, input reset, input clear,
+ input [35:0] f36_data,
+ input f36_src_rdy_i,
+ output f36_dst_rdy_o,
+
+ output reg [7:0] ll_data,
+ output ll_sof_n,
+ output ll_eof_n,
+ output ll_src_rdy_n,
+ input ll_dst_rdy_n,
+
+ output [31:0] debug);
+
+ wire ll_sof, ll_eof, ll_src_rdy;
+ assign ll_sof_n = ~ll_sof;
+ assign ll_eof_n = ~ll_eof;
+ assign ll_src_rdy_n = ~ll_src_rdy;
+ wire ll_dst_rdy = ~ll_dst_rdy_n;
+
+ wire f36_sof = f36_data[32];
+ wire f36_eof = f36_data[33];
+ wire f36_occ = f36_data[35:34];
+ wire advance, end_early;
+ reg [1:0] state;
+ assign debug = {29'b0,state};
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(advance)
+ if(ll_eof)
+ state <= 0;
+ else
+ state <= state + 1;
+
+ always @*
+ case(state)
+ 0 : ll_data = f36_data[31:24];
+ 1 : ll_data = f36_data[23:16];
+ 2 : ll_data = f36_data[15:8];
+ 3 : ll_data = f36_data[7:0];
+ default : ll_data = f36_data[31:24];
+ endcase // case (state)
+
+ assign ll_sof = (state==0) & f36_sof;
+ assign ll_eof = f36_eof & (((state==0)&(f36_occ==1)) |
+ ((state==1)&(f36_occ==2)) |
+ ((state==2)&(f36_occ==3)) |
+ (state==3));
+
+ assign ll_src_rdy = f36_src_rdy_i;
+
+ assign advance = ll_src_rdy & ll_dst_rdy;
+ assign f36_dst_rdy_o = advance & ((state==3)|ll_eof);
+ assign debug = state;
+
+endmodule // ll8_to_fifo36
diff --git a/fpga/usrp2/fifo/fifo_2clock.v b/fpga/usrp2/fifo/fifo_2clock.v
new file mode 100644
index 000000000..34c85ccb4
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo_2clock.v
@@ -0,0 +1,117 @@
+
+// FIXME ignores the AWIDTH (fifo size) parameter
+
+module fifo_2clock
+ #(parameter WIDTH=36, SIZE=6)
+ (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+ input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+ input arst);
+
+ wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels
+ wire full, empty, write, read;
+
+ assign dst_rdy_o = ~full;
+ assign src_rdy_o = ~empty;
+ assign write = src_rdy_i & dst_rdy_o;
+ assign read = src_rdy_o & dst_rdy_i;
+
+ generate
+ if(WIDTH==36)
+ if(SIZE==9)
+ fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+ (.rst(arst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if(SIZE==11)
+ fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk
+ (.rst(arst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if(SIZE==6)
+ fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk
+ (.rst(arst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else
+ fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+ (.rst(arst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if((WIDTH==19)|(WIDTH==18))
+ if(SIZE==4)
+ fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
+ (.rst(arst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ endgenerate
+
+ assign occupied = {{(16-SIZE-1){1'b0}},level_rclk};
+ assign space = ((1<<SIZE)+1)-level_wclk;
+
+endmodule // fifo_2clock
+
+/*
+`else
+ // ISE sucks, so the following doesn't work properly
+
+ reg [AWIDTH-1:0] wr_addr, rd_addr;
+ wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
+ wire [AWIDTH-1:0] next_rd_addr;
+ wire enb_read;
+
+ // Write side management
+ wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
+ always @(posedge wclk or posedge arst)
+ if(arst)
+ wr_addr <= 0;
+ else if(write)
+ wr_addr <= next_wr_addr;
+ assign full = (next_wr_addr == rd_addr_wclk);
+
+ // RAM for data storage. Data out is registered, complicating the
+ // read side logic
+ ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
+ (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
+ .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) );
+
+ // Read side management
+ reg data_valid;
+ assign empty = ~data_valid;
+ assign next_rd_addr = rd_addr + data_valid;
+ assign enb_read = read | ~data_valid;
+
+ always @(posedge rclk or posedge arst)
+ if(arst)
+ rd_addr <= 0;
+ else if(read)
+ rd_addr <= rd_addr + 1;
+
+ always @(posedge rclk or posedge arst)
+ if(arst)
+ data_valid <= 0;
+ else
+ if(read & (next_rd_addr == wr_addr_rclk))
+ data_valid <= 0;
+ else if(next_rd_addr != wr_addr_rclk)
+ data_valid <= 1;
+
+ // Send pointers across clock domains via gray code
+ gray_send #(.WIDTH(AWIDTH)) send_wr_addr
+ (.clk_in(wclk),.addr_in(wr_addr),
+ .clk_out(rclk),.addr_out(wr_addr_rclk) );
+
+ gray_send #(.WIDTH(AWIDTH)) send_rd_addr
+ (.clk_in(rclk),.addr_in(rd_addr),
+ .clk_out(wclk),.addr_out(rd_addr_wclk) );
+
+ // Generate fullness info, these are approximate and may be delayed
+ // and are only for higher-level flow control.
+ // Only full and empty are guaranteed exact.
+ always @(posedge wclk)
+ level_wclk <= wr_addr - rd_addr_wclk;
+ always @(posedge rclk)
+ level_rclk <= wr_addr_rclk - rd_addr;
+`endif
+endmodule // fifo_2clock
+
+*/
diff --git a/fpga/usrp2/fifo/fifo_2clock_cascade.v b/fpga/usrp2/fifo/fifo_2clock_cascade.v
new file mode 100644
index 000000000..5ce726977
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo_2clock_cascade.v
@@ -0,0 +1,35 @@
+
+module fifo_2clock_cascade
+ #(parameter WIDTH=32, SIZE=9)
+ (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+ input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+ input arst);
+
+ wire [WIDTH-1:0] data_int1, data_int2;
+ wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+ wire [SIZE-1:0] level_wclk, level_rclk;
+ wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied;
+ wire [15:0] l_space, l_occupied;
+
+ fifo_short #(.WIDTH(WIDTH)) shortfifo
+ (.clk(wclk), .reset(arst), .clear(0),
+ .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
+ .space(s1_space), .occupied(s1_occupied) );
+
+ fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
+ (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
+ .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
+ .arst(arst) );
+
+ fifo_short #(.WIDTH(WIDTH)) shortfifo2
+ (.clk(rclk), .reset(arst), .clear(0),
+ .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
+ .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+ .space(s2_space), .occupied(s2_occupied));
+
+ // Be conservative -- Only advertise space from input side of fifo, occupied from output side
+ assign space = {11'b0,s1_space} + l_space;
+ assign occupied = {11'b0,s2_occupied} + l_occupied;
+
+endmodule // fifo_2clock_cascade
diff --git a/fpga/usrp2/fifo/fifo_cascade.v b/fpga/usrp2/fifo/fifo_cascade.v
new file mode 100644
index 000000000..fdd8449bc
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo_cascade.v
@@ -0,0 +1,52 @@
+
+
+// This FIFO exists to provide an intermediate point for the data on its
+// long trek from one RAM (in the buffer pool) to another (in the longfifo)
+// The shortfifo is more flexible in its placement since it is based on
+// distributed RAM
+
+// This one has the shortfifo on both the in and out sides.
+module fifo_cascade
+ #(parameter WIDTH=32, SIZE=9)
+ (input clk, input reset, input clear,
+ input [WIDTH-1:0] datain,
+ input src_rdy_i,
+ output dst_rdy_o,
+ output [WIDTH-1:0] dataout,
+ output src_rdy_o,
+ input dst_rdy_i,
+ output [15:0] space,
+ output [15:0] occupied);
+
+ wire [WIDTH-1:0] data_int, data_int2;
+ wire src_rdy_1, dst_rdy_1, src_rdy_2, dst_rdy_2;
+
+ wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied;
+ wire [15:0] l_space, l_occupied;
+
+ fifo_short #(.WIDTH(WIDTH)) head_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout(data_int), .src_rdy_o(src_rdy_1), .dst_rdy_i(dst_rdy_1),
+ .space(s1_space),.occupied(s1_occupied) );
+
+ fifo_long #(.WIDTH(WIDTH),.SIZE(SIZE)) middle_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(data_int), .src_rdy_i(src_rdy_1), .dst_rdy_o(dst_rdy_1),
+ .dataout(data_int2), .src_rdy_o(src_rdy_2), .dst_rdy_i(dst_rdy_2),
+ .space(l_space),.occupied(l_occupied) );
+
+ fifo_short #(.WIDTH(WIDTH)) tail_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(data_int2), .src_rdy_i(src_rdy_2), .dst_rdy_o(dst_rdy_2),
+ .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+ .space(s2_space),.occupied(s2_occupied) );
+
+ assign space = {11'b0,s1_space} + {11'b0,s2_space} + l_space;
+ assign occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied;
+
+endmodule // cascadefifo2
+
+
+
+
diff --git a/fpga/usrp2/fifo/fifo_long.v b/fpga/usrp2/fifo/fifo_long.v
new file mode 100644
index 000000000..0426779f6
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo_long.v
@@ -0,0 +1,148 @@
+
+// FIFO intended to be interchangeable with shortfifo, but
+// based on block ram instead of SRL16's
+// only one clock domain
+
+// Port A is write port, Port B is read port
+
+module fifo_long
+ #(parameter WIDTH=32, SIZE=9)
+ (input clk, input reset, input clear,
+ input [WIDTH-1:0] datain,
+ input src_rdy_i,
+ output dst_rdy_o,
+ output [WIDTH-1:0] dataout,
+ output src_rdy_o,
+ input dst_rdy_i,
+
+ output reg [15:0] space,
+ output reg [15:0] occupied);
+
+ wire write = src_rdy_i & dst_rdy_o;
+ wire read = dst_rdy_i & src_rdy_o;
+ wire full, empty;
+
+ assign dst_rdy_o = ~full;
+ assign src_rdy_o = ~empty;
+
+ // Read side states
+ localparam EMPTY = 0;
+ localparam PRE_READ = 1;
+ localparam READING = 2;
+
+ reg [SIZE-1:0] wr_addr, rd_addr;
+ reg [1:0] read_state;
+
+ reg empty_reg, full_reg;
+ always @(posedge clk)
+ if(reset)
+ wr_addr <= 0;
+ else if(clear)
+ wr_addr <= 0;
+ else if(write)
+ wr_addr <= wr_addr + 1;
+
+ ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
+ ram (.clka(clk),
+ .ena(1'b1),
+ .wea(write),
+ .addra(wr_addr),
+ .dia(datain),
+ .doa(),
+
+ .clkb(clk),
+ .enb((read_state==PRE_READ)|read),
+ .web(0),
+ .addrb(rd_addr),
+ .dib(0),
+ .dob(dataout));
+
+ always @(posedge clk)
+ if(reset)
+ begin
+ read_state <= EMPTY;
+ rd_addr <= 0;
+ empty_reg <= 1;
+ end
+ else
+ if(clear)
+ begin
+ read_state <= EMPTY;
+ rd_addr <= 0;
+ empty_reg <= 1;
+ end
+ else
+ case(read_state)
+ EMPTY :
+ if(write)
+ begin
+ //rd_addr <= wr_addr;
+ read_state <= PRE_READ;
+ end
+ PRE_READ :
+ begin
+ read_state <= READING;
+ empty_reg <= 0;
+ rd_addr <= rd_addr + 1;
+ end
+
+ READING :
+ if(read)
+ if(rd_addr == wr_addr)
+ begin
+ empty_reg <= 1;
+ if(write)
+ read_state <= PRE_READ;
+ else
+ read_state <= EMPTY;
+ end
+ else
+ rd_addr <= rd_addr + 1;
+ endcase // case(read_state)
+
+ wire [SIZE-1:0] dont_write_past_me = rd_addr - 3;
+ wire becoming_full = wr_addr == dont_write_past_me;
+
+ always @(posedge clk)
+ if(reset)
+ full_reg <= 0;
+ else if(clear)
+ full_reg <= 0;
+ else if(read & ~write)
+ full_reg <= 0;
+ //else if(write & ~read & (wr_addr == (rd_addr-3)))
+ else if(write & ~read & becoming_full)
+ full_reg <= 1;
+
+ //assign empty = (read_state != READING);
+ assign empty = empty_reg;
+
+ // assign full = ((rd_addr - 1) == wr_addr);
+ assign full = full_reg;
+
+ //////////////////////////////////////////////
+ // space and occupied are for diagnostics only
+ // not guaranteed exact
+
+ localparam NUMLINES = (1<<SIZE)-2;
+ always @(posedge clk)
+ if(reset)
+ space <= NUMLINES;
+ else if(clear)
+ space <= NUMLINES;
+ else if(read & ~write)
+ space <= space + 1;
+ else if(write & ~read)
+ space <= space - 1;
+
+ always @(posedge clk)
+ if(reset)
+ occupied <= 0;
+ else if(clear)
+ occupied <= 0;
+ else if(read & ~write)
+ occupied <= occupied - 1;
+ else if(write & ~read)
+ occupied <= occupied + 1;
+
+endmodule // fifo_long
diff --git a/fpga/usrp2/fifo/fifo_new_tb.vcd b/fpga/usrp2/fifo/fifo_new_tb.vcd
new file mode 100644
index 000000000..796889e7d
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo_new_tb.vcd
@@ -0,0 +1,5506 @@
+$date
+ Thu Mar 19 17:21:11 2009
+$end
+$version
+ Icarus Verilog
+$end
+$timescale
+ 1ps
+$end
+$scope module fifo_new_tb $end
+$var wire 1 ! dst_rdy_f36i $end
+$var wire 36 " f36_in [35:0] $end
+$var wire 36 # i1 [35:0] $end
+$var wire 1 $ i1_dr $end
+$var wire 1 % i1_sr $end
+$var wire 19 & i2 [18:0] $end
+$var wire 1 ' i2_dr $end
+$var wire 1 ( i2_sr $end
+$var wire 19 ) i3 [18:0] $end
+$var wire 1 * i3_dr $end
+$var wire 1 + i3_sr $end
+$var wire 36 , i4 [35:0] $end
+$var wire 1 - i4_sr $end
+$var wire 8 . ll_data [7:0] $end
+$var wire 1 / ll_dst_rdy_n $end
+$var wire 1 0 ll_eof_n $end
+$var wire 1 1 ll_sof_n $end
+$var wire 1 2 ll_src_rdy_n $end
+$var reg 1 3 clear $end
+$var reg 1 4 clk $end
+$var reg 16 5 count [15:0] $end
+$var reg 1 6 dst_rdy_f36o $end
+$var reg 32 7 f36_data [31:0] $end
+$var reg 1 8 f36_eof $end
+$var reg 2 9 f36_occ [1:0] $end
+$var reg 1 : f36_sof $end
+$var reg 1 ; i4_dr $end
+$var reg 1 < rst $end
+$var reg 1 = src_rdy_f36i $end
+$scope module fifo_short1 $end
+$var wire 1 > clear $end
+$var wire 1 ? clk $end
+$var wire 36 @ datain [35:0] $end
+$var wire 36 A dataout [35:0] $end
+$var wire 1 $ dst_rdy_i $end
+$var wire 1 ! dst_rdy_o $end
+$var wire 1 B read $end
+$var wire 1 C reset $end
+$var wire 1 D src_rdy_i $end
+$var wire 1 % src_rdy_o $end
+$var wire 1 E write $end
+$var reg 4 F a [3:0] $end
+$var reg 1 G empty $end
+$var reg 1 H full $end
+$var reg 5 I occupied [4:0] $end
+$var reg 5 J space [4:0] $end
+$scope begin gen_srl16[0] $end
+$scope module srl16e $end
+$var wire 1 K A0 $end
+$var wire 1 L A1 $end
+$var wire 1 M A2 $end
+$var wire 1 N A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 O D $end
+$var wire 1 P Q $end
+$var reg 16 Q data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[1] $end
+$scope module srl16e $end
+$var wire 1 R A0 $end
+$var wire 1 S A1 $end
+$var wire 1 T A2 $end
+$var wire 1 U A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 V D $end
+$var wire 1 W Q $end
+$var reg 16 X data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[2] $end
+$scope module srl16e $end
+$var wire 1 Y A0 $end
+$var wire 1 Z A1 $end
+$var wire 1 [ A2 $end
+$var wire 1 \ A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 ] D $end
+$var wire 1 ^ Q $end
+$var reg 16 _ data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[3] $end
+$scope module srl16e $end
+$var wire 1 ` A0 $end
+$var wire 1 a A1 $end
+$var wire 1 b A2 $end
+$var wire 1 c A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 d D $end
+$var wire 1 e Q $end
+$var reg 16 f data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[4] $end
+$scope module srl16e $end
+$var wire 1 g A0 $end
+$var wire 1 h A1 $end
+$var wire 1 i A2 $end
+$var wire 1 j A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 k D $end
+$var wire 1 l Q $end
+$var reg 16 m data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[5] $end
+$scope module srl16e $end
+$var wire 1 n A0 $end
+$var wire 1 o A1 $end
+$var wire 1 p A2 $end
+$var wire 1 q A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
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diff --git a/fpga/usrp2/fifo/fifo_short.v b/fpga/usrp2/fifo/fifo_short.v
new file mode 100644
index 000000000..53a7603c7
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo_short.v
@@ -0,0 +1,95 @@
+
+module fifo_short
+ #(parameter WIDTH=32)
+ (input clk, input reset, input clear,
+ input [WIDTH-1:0] datain,
+ input src_rdy_i,
+ output dst_rdy_o,
+ output [WIDTH-1:0] dataout,
+ output src_rdy_o,
+ input dst_rdy_i,
+
+ output reg [4:0] space,
+ output reg [4:0] occupied);
+
+ reg full, empty;
+ wire write = src_rdy_i & dst_rdy_o;
+ wire read = dst_rdy_i & src_rdy_o;
+
+ assign dst_rdy_o = ~full;
+ assign src_rdy_o = ~empty;
+
+ reg [3:0] a;
+ genvar i;
+
+ generate
+ for (i=0;i<WIDTH;i=i+1)
+ begin : gen_srl16
+ SRL16E
+ srl16e(.Q(dataout[i]),
+ .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
+ .CE(write),.CLK(clk),.D(datain[i]));
+ end
+ endgenerate
+
+ always @(posedge clk)
+ if(reset)
+ begin
+ a <= 0;
+ empty <= 1;
+ full <= 0;
+ end
+ else if(clear)
+ begin
+ a <= 0;
+ empty <= 1;
+ full<= 0;
+ end
+ else if(read & ~write)
+ begin
+ full <= 0;
+ if(a==0)
+ empty <= 1;
+ else
+ a <= a - 1;
+ end
+ else if(write & ~read)
+ begin
+ empty <= 0;
+ if(~empty)
+ a <= a + 1;
+ if(a == 14)
+ full <= 1;
+ end
+
+ // NOTE will fail if you write into a full fifo or read from an empty one
+
+ //////////////////////////////////////////////////////////////
+ // space and occupied are used for diagnostics, not
+ // guaranteed correct
+
+ //assign space = full ? 0 : empty ? 16 : 15-a;
+ //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+ always @(posedge clk)
+ if(reset)
+ space <= 16;
+ else if(clear)
+ space <= 16;
+ else if(read & ~write)
+ space <= space + 1;
+ else if(write & ~read)
+ space <= space - 1;
+
+ always @(posedge clk)
+ if(reset)
+ occupied <= 0;
+ else if(clear)
+ occupied <= 0;
+ else if(read & ~write)
+ occupied <= occupied - 1;
+ else if(write & ~read)
+ occupied <= occupied + 1;
+
+endmodule // fifo_short
+
diff --git a/fpga/usrp2/fifo/fifo_spec.txt b/fpga/usrp2/fifo/fifo_spec.txt
new file mode 100644
index 000000000..133b9fa8e
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo_spec.txt
@@ -0,0 +1,36 @@
+
+
+FIFO and Buffer Interface Spec
+
+Buffer Interface Data Wires -- matches fifo36
+ DATA[31:0]
+ FLAGS[3:0]
+ Bit 0 SOP
+ Bit 1 EOP
+ If SOP=1 && EOP=1, OCC contains error flags
+ Bits 3:2 OCC[1:0] --> 00 = all 4 bytes
+ 01 = 1 byte
+ 10 = 2 bytes
+ 11 = 3 bytes
+
+fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]}
+ OCC same as buffer interface
+
+fifo19 --> {OCC,EOP,SOP,DATA[15:0]}
+ Doesn't fit well into BRAM, dist RAM ok
+ OCC = 1 means last word is half full
+ = 0 means last word is full
+
+fifo18 --> {EOP,SOP,DATA[15:0]}
+ No half-word capability? Should we drop sop instead?
+
+Control Wires - Data into FIFO
+ SRC_RDY_i Upstream has data for me
+ DST_RDY_o I have space
+ Transfer occurs if SRC_RDI_i && DST_RDY_o
+
+Control Wires - Data out of FIFO
+ SRC_RDY_o I have data for downstream
+ DST_RDY_i Downstream has space
+ Transfer occurs if SRC_RDI_o && DST_RDY_i
+
diff --git a/fpga/usrp2/fifo/fifo_tb.v b/fpga/usrp2/fifo/fifo_tb.v
new file mode 100644
index 000000000..f561df7fa
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo_tb.v
@@ -0,0 +1,158 @@
+module fifo_new_tb();
+
+ reg clk = 0;
+ reg rst = 1;
+ reg clear = 0;
+ initial #1000 rst = 0;
+ always #50 clk = ~clk;
+
+ reg [31:0] f36_data = 0;
+ reg [1:0] f36_occ = 0;
+ reg f36_sof = 0, f36_eof = 0;
+
+ wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+ reg src_rdy_f36i = 0;
+ wire dst_rdy_f36i;
+
+ wire [35:0] f36_out, f36_out2;
+ wire src_rdy_f36o;
+ reg dst_rdy_f36o = 0;
+
+ //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+ //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+
+ wire i1_sr, i1_dr;
+ wire i2_sr, i2_dr;
+ wire i3_sr, i3_dr;
+ reg i4_dr = 0;
+ wire i4_sr;
+
+ wire [35:0] i1, i4;
+ wire [18:0] i2, i3;
+
+ wire [7:0] ll_data;
+ wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+
+ fifo_short #(.WIDTH(36)) fifo_short1
+ (.clk(clk),.reset(rst),.clear(clear),
+ .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+ .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+
+ fifo36_to_fifo19 fifo36_to_fifo19
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
+ .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
+
+ fifo19_to_ll8 fifo19_to_ll8
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
+ .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+ .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
+
+ ll8_to_fifo19 ll8_to_fifo19
+ (.clk(clk),.reset(rst),.clear(clear),
+ .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+ .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
+ .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
+
+ fifo19_to_fifo36 fifo19_to_fifo36
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
+ .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
+
+ task ReadFromFIFO36;
+ begin
+ $display("Read from FIFO36");
+ #1 i4_dr <= 1;
+ while(1)
+ begin
+ while(~i4_sr)
+ @(posedge clk);
+ $display("Read: %h",i4);
+ @(posedge clk);
+ end
+ end
+ endtask // ReadFromFIFO36
+
+ reg [15:0] count;
+ task PutPacketInFIFO36;
+ input [31:0] data_start;
+ input [31:0] data_len;
+ begin
+ count <= 4;
+ src_rdy_f36i <= 1;
+ f36_data <= data_start;
+ f36_sof <= 1;
+ f36_eof <= 0;
+ f36_occ <= 0;
+
+ $display("Put Packet in FIFO36");
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ $display("PPI_FIFO36: Entered First Line");
+ f36_sof <= 0;
+ while(count+4 < data_len)
+ begin
+ f36_data <= f36_data + 32'h01010101;
+ count <= count + 4;
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ $display("PPI_FIFO36: Entered New Line");
+ end
+ f36_data <= f36_data + 32'h01010101;
+ f36_eof <= 1;
+ if(count + 4 == data_len)
+ f36_occ <= 0;
+ else if(count + 3 == data_len)
+ f36_occ <= 3;
+ else if(count + 2 == data_len)
+ f36_occ <= 2;
+ else
+ f36_occ <= 1;
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ f36_occ <= 0;
+ f36_eof <= 0;
+ f36_data <= 0;
+ src_rdy_f36i <= 0;
+ $display("PPI_FIFO36: Entered Last Line");
+ end
+ endtask // PutPacketInFIFO36
+
+ initial $dumpfile("fifo_new_tb.vcd");
+ initial $dumpvars(0,fifo_new_tb);
+
+ initial
+ begin
+ @(negedge rst);
+ //#10000;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ ReadFromFIFO36;
+ end
+
+ initial
+ begin
+ @(negedge rst);
+ @(posedge clk);
+ @(posedge clk);
+ PutPacketInFIFO36(32'hA0B0C0D0,12);
+ @(posedge clk);
+ @(posedge clk);
+ #10000;
+ @(posedge clk);
+ PutPacketInFIFO36(32'hE0F0A0B0,36);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ end
+
+ initial #20000 $finish;
+endmodule // longfifo_tb
diff --git a/fpga/usrp2/fifo/ll8_shortfifo.v b/fpga/usrp2/fifo/ll8_shortfifo.v
new file mode 100644
index 000000000..39ada9a4f
--- /dev/null
+++ b/fpga/usrp2/fifo/ll8_shortfifo.v
@@ -0,0 +1,13 @@
+
+
+module ll8_shortfifo
+ (input clk, input reset, input clear,
+ input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o,
+ output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i);
+
+ fifo_short #(.WIDTH(11)) fifo_short
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+
+endmodule // ll8_shortfifo
diff --git a/fpga/usrp2/fifo/ll8_to_fifo19.v b/fpga/usrp2/fifo/ll8_to_fifo19.v
new file mode 100644
index 000000000..af3b91afb
--- /dev/null
+++ b/fpga/usrp2/fifo/ll8_to_fifo19.v
@@ -0,0 +1,73 @@
+
+module ll8_to_fifo19
+ (input clk, input reset, input clear,
+ input [7:0] ll_data,
+ input ll_sof_n,
+ input ll_eof_n,
+ input ll_src_rdy_n,
+ output ll_dst_rdy_n,
+
+ output [18:0] f19_data,
+ output f19_src_rdy_o,
+ input f19_dst_rdy_i );
+
+ localparam XFER_EMPTY = 0;
+ localparam XFER_HALF = 1;
+ localparam XFER_HALF_WRITE = 3;
+
+ // Why anybody would use active low in an FPGA is beyond me...
+ wire ll_sof = ~ll_sof_n;
+ wire ll_eof = ~ll_eof_n;
+ wire ll_src_rdy = ~ll_src_rdy_n;
+ wire ll_dst_rdy;
+ assign ll_dst_rdy_n = ~ll_dst_rdy;
+
+ wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i;
+ wire xfer_in = ll_src_rdy & ll_dst_rdy;
+
+ reg hold_sof;
+ wire f19_sof, f19_eof, f19_occ;
+
+ reg [1:0] state;
+ reg [7:0] hold_reg;
+
+ always @(posedge clk)
+ if(ll_src_rdy & (state==XFER_EMPTY))
+ hold_reg <= ll_data;
+
+ always @(posedge clk)
+ if(ll_sof & (state==XFER_EMPTY))
+ hold_sof <= 1;
+ else if(xfer_out)
+ hold_sof <= 0;
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= XFER_EMPTY;
+ else
+ case(state)
+ XFER_EMPTY :
+ if(ll_src_rdy)
+ if(ll_eof)
+ state <= XFER_HALF_WRITE;
+ else
+ state <= XFER_HALF;
+ XFER_HALF :
+ if(ll_src_rdy & f19_dst_rdy_i)
+ state <= XFER_EMPTY;
+ XFER_HALF_WRITE :
+ if(f19_dst_rdy_i)
+ state <= XFER_EMPTY;
+ endcase // case (state)
+
+ assign ll_dst_rdy = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i);
+ assign f19_src_rdy_o = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy);
+
+ assign f19_sof = hold_sof | (ll_sof & (state==XFER_HALF));
+ assign f19_eof = (state == XFER_HALF_WRITE) | ll_eof;
+ assign f19_occ = (state == XFER_HALF_WRITE);
+
+ assign f19_data = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data};
+
+endmodule // ll8_to_fifo19
+
diff --git a/fpga/usrp2/fifo/ll8_to_fifo36.v b/fpga/usrp2/fifo/ll8_to_fifo36.v
new file mode 100644
index 000000000..108daa903
--- /dev/null
+++ b/fpga/usrp2/fifo/ll8_to_fifo36.v
@@ -0,0 +1,97 @@
+
+module ll8_to_fifo36
+ (input clk, input reset, input clear,
+ input [7:0] ll_data,
+ input ll_sof_n,
+ input ll_eof_n,
+ input ll_src_rdy_n,
+ output ll_dst_rdy_n,
+
+ output [35:0] f36_data,
+ output f36_src_rdy_o,
+ input f36_dst_rdy_i );
+
+ wire f36_write = f36_src_rdy_o & f36_dst_rdy_i;
+
+ // Why anybody would use active low in an FPGA is beyond me...
+ wire ll_sof = ~ll_sof_n;
+ wire ll_eof = ~ll_eof_n;
+ wire ll_src_rdy = ~ll_src_rdy_n;
+ wire ll_dst_rdy;
+ assign ll_dst_rdy_n = ~ll_dst_rdy;
+
+ reg f36_sof, f36_eof;
+ reg [1:0] f36_occ;
+
+
+ reg [2:0] state;
+ reg [7:0] dat0, dat1, dat2, dat3;
+
+ always @(posedge clk)
+ if(ll_src_rdy & ((state==0)|f36_write))
+ f36_sof <= ll_sof;
+
+ always @(posedge clk)
+ if(ll_src_rdy & ((state !=4)|f36_write))
+ f36_eof <= ll_eof;
+
+ always @(posedge clk)
+ if(ll_eof)
+ f36_occ <= state[1:0] + 1;
+ else
+ f36_occ <= 0;
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(ll_src_rdy)
+ case(state)
+ 0 :
+ if(ll_eof)
+ state <= 4;
+ else
+ state <= 1;
+ 1 :
+ if(ll_eof)
+ state <= 4;
+ else
+ state <= 2;
+ 2 :
+ if(ll_eof)
+ state <= 4;
+ else
+ state <= 3;
+ 3 : state <= 4;
+ 4 :
+ if(f36_dst_rdy_i)
+ if(ll_eof)
+ state <= 4;
+ else
+ state <= 1;
+ endcase // case(state)
+ else
+ if(f36_write)
+ state <= 0;
+
+ always @(posedge clk)
+ if(ll_src_rdy & (state==3))
+ dat3 <= ll_data;
+
+ always @(posedge clk)
+ if(ll_src_rdy & (state==2))
+ dat2 <= ll_data;
+
+ always @(posedge clk)
+ if(ll_src_rdy & (state==1))
+ dat1 <= ll_data;
+
+ always @(posedge clk)
+ if(ll_src_rdy & ((state==0) | f36_write))
+ dat0 <= ll_data;
+
+ assign ll_dst_rdy = f36_dst_rdy_i | (state != 4);
+ assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3}; // FIXME endianess
+ assign f36_src_rdy_o = (state == 4);
+
+endmodule // ll8_to_fifo36
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