diff options
Diffstat (limited to 'fpga/usrp2/fifo')
| -rw-r--r-- | fpga/usrp2/fifo/fifo19_to_fifo36.v | 55 | ||||
| -rw-r--r-- | fpga/usrp2/fifo/fifo36_to_fifo19.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/fifo/fifo_19to36_tb.v | 82 |
3 files changed, 114 insertions, 25 deletions
diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v index 2f530109f..ae2edddc7 100644 --- a/fpga/usrp2/fifo/fifo19_to_fifo36.v +++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v @@ -36,42 +36,49 @@ module fifo19_to_fifo36 if(f19_src_rdy_i & ((state != 2)|xfer_out)) f36_eof <= f19_eof; - always @(posedge clk) // FIXME check this - if(f19_eof) - f36_occ <= {state[0],f19_occ}; - else - f36_occ <= 0; - always @(posedge clk) if(reset) - state <= 0; + begin + state <= 0; + f36_occ <= 0; + end else if(f19_src_rdy_i) case(state) 0 : - if(f19_eof) - state <= 2; - else - state <= 1; + begin + dat0 <= f19_datain; + if(f19_eof) + begin + state <= 2; + f36_occ <= f19_occ ? 2'b01 : 2'b10; + end + else + state <= 1; + end 1 : - state <= 2; + begin + dat1 <= f19_datain; + state <= 2; + if(f19_eof) + f36_occ <= f19_occ ? 2'b11 : 2'b00; + end 2 : if(xfer_out) - if(~f19_eof) - state <= 1; - // remain in state 2 if we are at eof + begin + dat0 <= f19_datain; + if(f19_eof) // remain in state 2 if we are at eof + f36_occ <= f19_occ ? 2'b01 : 2'b10; + else + state <= 1; + end endcase // case(state) else if(xfer_out) - state <= 0; - - always @(posedge clk) - if(f19_src_rdy_i & (state==1)) - dat1 <= f19_datain; - - always @(posedge clk) - if(f19_src_rdy_i & ((state==0) | xfer_out)) - dat0 <= f19_datain; + begin + state <= 0; + f36_occ <= 0; + end assign f19_dst_rdy_o = xfer_out | (state != 2); assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} : diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v index 517a2a476..e016fe2c6 100644 --- a/fpga/usrp2/fifo/fifo36_to_fifo19.v +++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v @@ -16,7 +16,7 @@ module fifo36_to_fifo19 wire f36_sof = f36_datain[32]; wire f36_eof = f36_datain[33]; - wire f36_occ = f36_datain[35:34]; + wire [1:0] f36_occ = f36_datain[35:34]; reg phase; diff --git a/fpga/usrp2/fifo/fifo_19to36_tb.v b/fpga/usrp2/fifo/fifo_19to36_tb.v new file mode 100644 index 000000000..c585392c3 --- /dev/null +++ b/fpga/usrp2/fifo/fifo_19to36_tb.v @@ -0,0 +1,82 @@ +module fifo_tb(); + + reg clk = 0; + reg rst = 1; + reg clear = 0; + initial #1000 rst = 0; + always #50 clk = ~clk; + + reg [18:0] f19a; + wire [18:0] f19b, f19c, f19d; + wire [35:0] f36a, f36b; + + reg f19a_sr = 0; + wire f19b_sr, f19c_sr, f19d_sr, f36a_sr, f36b_sr; + wire f19a_dr, f19b_dr, f19c_dr, f19d_dr, f36a_dr, f36b_dr; + + fifo_short #(.WIDTH(19)) fifo_short1 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f19a),.src_rdy_i(f19a_sr),.dst_rdy_o(f19a_dr), + .dataout(f19b),.src_rdy_o(f19b_sr),.dst_rdy_i(f19b_dr) ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk),.reset(rst),.clear(clear), + .f19_datain(f19b),.f19_src_rdy_i(f19b_sr),.f19_dst_rdy_o(f19b_dr), + .f36_dataout(f36a),.f36_src_rdy_o(f36a_sr),.f36_dst_rdy_i(f36a_dr) ); + + fifo_short #(.WIDTH(36)) fifo_short2 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f36a),.src_rdy_i(f36a_sr),.dst_rdy_o(f36a_dr), + .dataout(f36b),.src_rdy_o(f36b_sr),.dst_rdy_i(f36b_dr) ); + + fifo36_to_fifo19 fifo36_to_fifo19 + (.clk(clk),.reset(rst),.clear(clear), + .f36_datain(f36b),.f36_src_rdy_i(f36b_sr),.f36_dst_rdy_o(f36b_dr), + .f19_dataout(f19c),.f19_src_rdy_o(f19c_sr),.f19_dst_rdy_i(f19c_dr) ); + + fifo_short #(.WIDTH(19)) fifo_short3 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f19c),.src_rdy_i(f19c_sr),.dst_rdy_o(f19c_dr), + .dataout(f19d),.src_rdy_o(f19d_sr),.dst_rdy_i(f19d_dr) ); + + assign f19d_dr = 1; + + always @(posedge clk) + if(f19a_sr & f19a_dr) + $display("18IN: %h", f19a); + + always @(posedge clk) + if(f19d_sr & f19d_dr) + $display(" 18OUT: %h", f19d); + + always @(posedge clk) + if(f36b_sr & f36b_dr) + $display(" 36: %h", f36b); + + initial $dumpfile("fifo_tb.vcd"); + initial $dumpvars(0,fifo_tb); + + initial + begin + @(negedge rst); + @(posedge clk); + repeat (2) + begin + f19a <= 19'h1_AA01; + f19a_sr <= 1; + @(posedge clk); + f19a <= 19'h0_AA02; + repeat (4) + begin + @(posedge clk); + f19a <= f19a + 1; + end + f19a[18:16] <= 3'b010; + @(posedge clk); + f19a_sr <= 0; + f19a <= 19'h7_FFFF; + @(posedge clk); + end + #20000 $finish; + end +endmodule // longfifo_tb |