diff options
Diffstat (limited to 'fpga/usrp2/fifo/fifo_2clock.v')
| -rw-r--r-- | fpga/usrp2/fifo/fifo_2clock.v | 36 |
1 files changed, 29 insertions, 7 deletions
diff --git a/fpga/usrp2/fifo/fifo_2clock.v b/fpga/usrp2/fifo/fifo_2clock.v index 34c85ccb4..756ad508f 100644 --- a/fpga/usrp2/fifo/fifo_2clock.v +++ b/fpga/usrp2/fifo/fifo_2clock.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // FIXME ignores the AWIDTH (fifo size) parameter @@ -14,7 +31,8 @@ module fifo_2clock assign src_rdy_o = ~empty; assign write = src_rdy_i & dst_rdy_o; assign read = src_rdy_o & dst_rdy_i; - + wire dummy; + generate if(WIDTH==36) if(SIZE==9) @@ -37,12 +55,16 @@ module fifo_2clock (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if((WIDTH==19)|(WIDTH==18)) - if(SIZE==4) - fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk - (.rst(arst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==19) & (SIZE==4)) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==18) & (SIZE==4)) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din({1'b0,datain}),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout({dummy,dataout}),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; |