diff options
Diffstat (limited to 'fpga/usrp2/fifo/crossbar36.v')
| -rw-r--r-- | fpga/usrp2/fifo/crossbar36.v | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/fpga/usrp2/fifo/crossbar36.v b/fpga/usrp2/fifo/crossbar36.v index d90f5659c..2a046d8bf 100644 --- a/fpga/usrp2/fifo/crossbar36.v +++ b/fpga/usrp2/fifo/crossbar36.v @@ -9,6 +9,8 @@ module crossbar36 output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i); reg cross_int, active0, active1; + wire active0_next = (src0_rdy_i & dst0_rdy_o)? ~data0_i[33] : active0; + wire active1_next = (src1_rdy_i & dst1_rdy_o)? ~data1_i[33] : active1; assign data0_o = cross_int ? data1_i : data0_i; assign data1_o = cross_int ? data0_i : data1_i; @@ -22,19 +24,19 @@ module crossbar36 always @(posedge clk) if(reset | clear) active0 <= 0; - else if(src0_rdy_i & dst0_rdy_o) - active0 <= ~data0_i[33]; + else + active0 <= active0_next; always @(posedge clk) if(reset | clear) active1 <= 0; - else if(src1_rdy_i & dst1_rdy_o) - active1 <= ~data1_i[33]; + else + active1 <= active1_next; always @(posedge clk) if(reset | clear) cross_int <= 0; - else if(~active0 & ~active1) + else if(~active0_next & ~active1_next) cross_int <= cross; endmodule // crossbar36 |