diff options
Diffstat (limited to 'fpga/usrp2/extramfifo/fifo_extram_tb.build')
| -rwxr-xr-x | fpga/usrp2/extramfifo/fifo_extram_tb.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.build b/fpga/usrp2/extramfifo/fifo_extram_tb.build new file mode 100755 index 000000000..5607c8691 --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram_tb.build @@ -0,0 +1 @@ +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v |