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-rwxr-xr-xfpga/usrp2/extramfifo/fifo_extram_tb.build1
1 files changed, 0 insertions, 1 deletions
diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.build b/fpga/usrp2/extramfifo/fifo_extram_tb.build
deleted file mode 100755
index 5607c8691..000000000
--- a/fpga/usrp2/extramfifo/fifo_extram_tb.build
+++ /dev/null
@@ -1 +0,0 @@
-iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v