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-rw-r--r--fpga/usrp2/extramfifo/ext_fifo_tb.cmd12
1 files changed, 12 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.cmd b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd
new file mode 100644
index 000000000..521f88f21
--- /dev/null
+++ b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd
@@ -0,0 +1,12 @@
+/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v
+-y .
+-y ../coregen/
+-y ../fifo
+-y ../models
+-y /home/ianb/usrp-fpga/usrp2/sdr_lib
+-y /home/ianb/usrp-fpga/usrp2/control_lib
+-y /home/ianb/usrp-fpga/usrp2/models
+-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims
+-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src
+-y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib
+