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-rw-r--r--fpga/usrp2/control_lib/Makefile.srcs4
-rw-r--r--fpga/usrp2/control_lib/bootram.v250
-rw-r--r--fpga/usrp2/control_lib/quad_uart.v71
-rw-r--r--fpga/usrp2/control_lib/ram_harvard2.v77
-rw-r--r--fpga/usrp2/control_lib/s3a_icap_wb.v59
-rw-r--r--fpga/usrp2/control_lib/v5icap_wb.v54
6 files changed, 515 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs
index 383ed97d8..d3bb7e2c8 100644
--- a/fpga/usrp2/control_lib/Makefile.srcs
+++ b/fpga/usrp2/control_lib/Makefile.srcs
@@ -21,6 +21,7 @@ nsgpio.v \
ram_2port.v \
ram_harv_cache.v \
ram_harvard.v \
+ram_harvard2.v \
ram_loader.v \
setting_reg.v \
settings_bus.v \
@@ -29,6 +30,7 @@ srl.v \
system_control.v \
wb_1master.v \
wb_readback_mux.v \
+quad_uart.v \
simple_uart.v \
simple_uart_tx.v \
simple_uart_rx.v \
@@ -42,6 +44,8 @@ pic.v \
longfifo.v \
shortfifo.v \
medfifo.v \
+s3a_icap_wb.v \
+bootram.v \
nsgpio16LE.v \
settings_bus_16LE.v \
atr_controller16.v \
diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v
new file mode 100644
index 000000000..668012504
--- /dev/null
+++ b/fpga/usrp2/control_lib/bootram.v
@@ -0,0 +1,250 @@
+
+// Boot RAM for S3A, 8KB, dual port
+
+// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM
+// Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1
+
+module bootram
+ (input clk, input reset,
+ input [12:0] if_adr,
+ output [31:0] if_data,
+
+ input [12:0] dwb_adr_i,
+ input [31:0] dwb_dat_i,
+ output [31:0] dwb_dat_o,
+ input dwb_we_i,
+ output reg dwb_ack_o,
+ input dwb_stb_i,
+ input [3:0] dwb_sel_i);
+
+ wire [31:0] DOA0, DOA1, DOA2, DOA3;
+ wire [31:0] DOB0, DOB1, DOB2, DOB3;
+ wire ENB0, ENB1, ENB2, ENB3;
+ wire [3:0] WEB;
+
+ reg [1:0] delayed_if_bank;
+ always @(posedge clk)
+ delayed_if_bank <= if_adr[12:11];
+
+ assign if_data = delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0);
+ assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0);
+
+ always @(posedge clk)
+ if(reset)
+ dwb_ack_o <= 0;
+ else
+ dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
+
+ assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00);
+ assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01);
+ assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10);
+ assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11);
+
+ assign WEB = {4{dwb_we_i}} & dwb_sel_i;
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM0
+ (.DOA(DOA0), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB0), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB0), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM1
+ (.DOA(DOA1), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB1), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB1), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM2
+ (.DOA(DOA2), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB2), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB2), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM3
+ (.DOA(DOA3), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB3), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB3), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+endmodule // bootram
+
+/*
+ // The following INIT_xx declarations specify the initial contents of the RAM
+ // Address 0 to 127
+ .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // Address 128 to 255
+ .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // Address 256 to 383
+ .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // Address 384 to 511
+ .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // The next set of INITP_xx are for the parity bits
+ // Address 0 to 127
+ .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ // Address 128 to 255
+ .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ // Address 256 to 383
+ .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ // Address 384 to 511
+ .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000)
+*/
diff --git a/fpga/usrp2/control_lib/quad_uart.v b/fpga/usrp2/control_lib/quad_uart.v
new file mode 100644
index 000000000..afa6fae1d
--- /dev/null
+++ b/fpga/usrp2/control_lib/quad_uart.v
@@ -0,0 +1,71 @@
+
+module quad_uart
+ #(parameter TXDEPTH = 1,
+ parameter RXDEPTH = 1)
+ (input clk_i, input rst_i,
+ input we_i, input stb_i, input cyc_i, output reg ack_o,
+ input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+ output [3:0] rx_int_o, output [3:0] tx_int_o,
+ output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o
+ );
+
+ // Register Map
+ localparam SUART_CLKDIV = 0;
+ localparam SUART_TXLEVEL = 1;
+ localparam SUART_RXLEVEL = 2;
+ localparam SUART_TXCHAR = 3;
+ localparam SUART_RXCHAR = 4;
+
+ wire wb_acc = cyc_i & stb_i; // WISHBONE access
+ wire wb_wr = wb_acc & we_i; // WISHBONE write access
+
+ reg [15:0] clkdiv[0:3];
+ wire [7:0] rx_char[0:3];
+ wire [3:0] tx_fifo_full, rx_fifo_empty;
+ wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3];
+
+ always @(posedge clk_i)
+ if (rst_i)
+ ack_o <= 1'b0;
+ else
+ ack_o <= wb_acc & ~ack_o;
+
+ integer i;
+ always @(posedge clk_i)
+ if (rst_i)
+ for(i=0;i<4;i=i+1)
+ clkdiv[i] <= 0;
+ else if (wb_wr)
+ case(adr_i[2:0])
+ SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0];
+ endcase // case(adr_i)
+
+ always @(posedge clk_i)
+ case (adr_i[2:0])
+ SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]];
+ SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]];
+ SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]];
+ endcase // case(adr_i)
+
+ genvar j;
+ generate
+ for(j=0;j<4;j=j+1)
+ begin : gen_uarts
+ simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
+ (.clk(clk_i),.rst(rst_i),
+ .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)),
+ .fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]),
+ .clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j]));
+
+ simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
+ (.clk(clk_i),.rst(rst_i),
+ .fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)),
+ .fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]),
+ .clkdiv(clkdiv[j]),.rx(rx_i[j]));
+ end // block: gen_uarts
+ endgenerate
+
+ assign tx_int_o = ~tx_fifo_full; // Interrupt for those that have space
+ assign rx_int_o = ~rx_fifo_empty; // Interrupt for those that have data
+
+endmodule // quad_uart
diff --git a/fpga/usrp2/control_lib/ram_harvard2.v b/fpga/usrp2/control_lib/ram_harvard2.v
new file mode 100644
index 000000000..67777af2a
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_harvard2.v
@@ -0,0 +1,77 @@
+
+
+// Dual ported, Harvard architecture
+
+module ram_harvard2
+ #(parameter AWIDTH=15,
+ parameter RAM_SIZE=32768)
+ (input wb_clk_i,
+ input wb_rst_i,
+ // Instruction fetch port.
+ input [AWIDTH-1:0] if_adr,
+ output reg [31:0] if_data,
+ // Data access port.
+ input [AWIDTH-1:0] dwb_adr_i,
+ input [31:0] dwb_dat_i,
+ output reg [31:0] dwb_dat_o,
+ input dwb_we_i,
+ output dwb_ack_o,
+ input dwb_stb_i,
+ input [3:0] dwb_sel_i);
+
+ reg ack_d1;
+ reg stb_d1;
+
+ assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ ack_d1 <= 1'b0;
+ else
+ ack_d1 <= dwb_ack_o;
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ stb_d1 <= 0;
+ else
+ stb_d1 <= dwb_stb_i;
+
+ reg [7:0] ram0 [0:(RAM_SIZE/4)-1];
+ reg [7:0] ram1 [0:(RAM_SIZE/4)-1];
+ reg [7:0] ram2 [0:(RAM_SIZE/4)-1];
+ reg [7:0] ram3 [0:(RAM_SIZE/4)-1];
+
+ // Port 1, Read only
+ always @(posedge wb_clk_i)
+ if_data[31:24] <= ram3[if_adr[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if_data[23:16] <= ram2[if_adr[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if_data[15:8] <= ram1[if_adr[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if_data[7:0] <= ram0[if_adr[AWIDTH-1:2]];
+
+ // Port 2, R/W
+ always @(posedge wb_clk_i)
+ if(dwb_stb_i) dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if(dwb_stb_i) dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if(dwb_stb_i) dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if(dwb_stb_i) dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]];
+
+ always @(posedge wb_clk_i)
+ if(dwb_we_i & dwb_stb_i & dwb_sel_i[3])
+ ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24];
+ always @(posedge wb_clk_i)
+ if(dwb_we_i & dwb_stb_i & dwb_sel_i[2])
+ ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16];
+ always @(posedge wb_clk_i)
+ if(dwb_we_i & dwb_stb_i & dwb_sel_i[1])
+ ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8];
+ always @(posedge wb_clk_i)
+ if(dwb_we_i & dwb_stb_i & dwb_sel_i[0])
+ ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0];
+
+endmodule // ram_harvard
diff --git a/fpga/usrp2/control_lib/s3a_icap_wb.v b/fpga/usrp2/control_lib/s3a_icap_wb.v
new file mode 100644
index 000000000..83d9f775e
--- /dev/null
+++ b/fpga/usrp2/control_lib/s3a_icap_wb.v
@@ -0,0 +1,59 @@
+
+
+module s3a_icap_wb
+ (input clk, input reset,
+ input cyc_i, input stb_i, input we_i, output ack_o,
+ input [31:0] dat_i, output [31:0] dat_o);//, output [31:0] debug_out);
+
+ assign dat_o[31:8] = 24'd0;
+
+ wire BUSY, CE, WRITE, ICAPCLK;
+
+ //changed this to gray-ish code to prevent glitching
+ reg [2:0] icap_state;
+ localparam ICAP_IDLE = 0;
+ localparam ICAP_WR0 = 1;
+ localparam ICAP_WR1 = 5;
+ localparam ICAP_RD0 = 2;
+ localparam ICAP_RD1 = 3;
+
+ always @(posedge clk)
+ if(reset)
+ icap_state <= ICAP_IDLE;
+ else
+ case(icap_state)
+ ICAP_IDLE :
+ begin
+ if(stb_i & cyc_i)
+ if(we_i)
+ icap_state <= ICAP_WR0;
+ else
+ icap_state <= ICAP_RD0;
+ end
+ ICAP_WR0 :
+ icap_state <= ICAP_WR1;
+ ICAP_WR1 :
+ icap_state <= ICAP_IDLE;
+ ICAP_RD0 :
+ icap_state <= ICAP_RD1;
+ ICAP_RD1 :
+ icap_state <= ICAP_IDLE;
+ endcase // case (icap_state)
+
+ assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
+ assign CE = (icap_state == ICAP_WR0) | (icap_state == ICAP_RD0);
+ assign ICAPCLK = CE & (~clk);
+
+ assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
+ //assign debug_out = {17'd0, BUSY, dat_i[7:0], ~CE, ICAPCLK, ~WRITE, icap_state};
+
+ ICAP_SPARTAN3A ICAP_SPARTAN3A_inst
+ (.BUSY(BUSY), // Busy output
+ .O(dat_o[7:0]), // 32-bit data output
+ .CE(~CE), // Clock enable input
+ .CLK(ICAPCLK), // Clock input
+ .I(dat_i[7:0]), // 32-bit data input
+ .WRITE(~WRITE) // Write input
+ );
+
+endmodule // s3a_icap_wb
diff --git a/fpga/usrp2/control_lib/v5icap_wb.v b/fpga/usrp2/control_lib/v5icap_wb.v
new file mode 100644
index 000000000..c8800285a
--- /dev/null
+++ b/fpga/usrp2/control_lib/v5icap_wb.v
@@ -0,0 +1,54 @@
+
+
+module v5icap_wb
+ (input clk, input reset,
+ input cyc_i, input stb_i, input we_i, output ack_o,
+ input [31:0] dat_i, output [31:0] dat_o);
+
+ wire BUSY, CE, WRITE;
+
+ reg [2:0] icap_state;
+ localparam ICAP_IDLE = 0;
+ localparam ICAP_WR0 = 1;
+ localparam ICAP_WR1 = 2;
+ localparam ICAP_RD0 = 3;
+ localparam ICAP_RD1 = 4;
+
+ always @(posedge clk)
+ if(reset)
+ icap_state <= ICAP_IDLE;
+ else
+ case(icap_state)
+ ICAP_IDLE :
+ begin
+ if(stb_i & cyc_i)
+ if(we_i)
+ icap_state <= ICAP_WR0;
+ else
+ icap_state <= ICAP_RD0;
+ end
+ ICAP_WR0 :
+ icap_state <= ICAP_WR1;
+ ICAP_WR1 :
+ icap_state <= ICAP_IDLE;
+ ICAP_RD0 :
+ icap_state <= ICAP_RD1;
+ ICAP_RD1 :
+ icap_state <= ICAP_IDLE;
+ endcase // case (icap_state)
+
+ assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
+ assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0);
+
+ assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
+
+ ICAP_VIRTEX5 #(.ICAP_WIDTH("X32")) ICAP_VIRTEX5_inst
+ (.BUSY(BUSY), // Busy output
+ .O(dat_o), // 32-bit data output
+ .CE(~CE), // Clock enable input
+ .CLK(clk), // Clock input
+ .I(dat_i), // 32-bit data input
+ .WRITE(~WRITE) // Write input
+ );
+
+endmodule // v5icap_wb
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