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-rw-r--r--fpga/usrp2/control_lib/mux_32_4.v13
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diff --git a/fpga/usrp2/control_lib/mux_32_4.v b/fpga/usrp2/control_lib/mux_32_4.v
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+++ b/fpga/usrp2/control_lib/mux_32_4.v
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+
+
+module mux_32_4
+ (input [1:0] sel,
+ input [31:0] in0,
+ input [31:0] in1,
+ input [31:0] in2,
+ input [31:0] in3,
+ output [31:0] out);
+
+ assign out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0);
+
+endmodule // mux_32_4