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-rw-r--r--fpga/usrp2/control_lib/atr_controller.v7
1 files changed, 5 insertions, 2 deletions
diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v
index 2cef8ba2b..ee8b260c5 100644
--- a/fpga/usrp2/control_lib/atr_controller.v
+++ b/fpga/usrp2/control_lib/atr_controller.v
@@ -44,8 +44,11 @@ module atr_controller
atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
end // if (we_i & stb_i & cyc_i)
- always @(posedge clk_i)
- dat_o <= atr_ram[adr_i[5:2]];
+ // Removing readback allows ram to be synthesized as LUTs instead of regs
+ //always @(posedge clk_i)
+ // dat_o <= atr_ram[adr_i[5:2]];
+ always
+ dat_o <= 32'd0;
always @(posedge clk_i)
ack_o <= stb_i & cyc_i & ~ack_o;