1 files changed, 17 insertions, 0 deletions
diff --git a/fpga/usrp1/models/bustri.v b/fpga/usrp1/models/bustri.v
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index 000000000..6e5a0f74c
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+++ b/fpga/usrp1/models/bustri.v
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+
+// Model for tristate bus on altera
+// FIXME do we really need to use a megacell for this?
+
+module bustri (data,
+	       enabledt,
+	       tridata);
+   
+   input [15:0]  data;
+   input 	 enabledt;
+   inout [15:0]  tridata;
+   
+   assign 	 tridata = enabledt ? data :16'bz;
+   
+endmodule // bustri
+
+