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Diffstat (limited to 'fpga/usrp1/megacells/pll_bb.v')
| -rw-r--r-- | fpga/usrp1/megacells/pll_bb.v | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/fpga/usrp1/megacells/pll_bb.v b/fpga/usrp1/megacells/pll_bb.v deleted file mode 100644 index debadaa25..000000000 --- a/fpga/usrp1/megacells/pll_bb.v +++ /dev/null @@ -1,29 +0,0 @@ -//Copyright (C) 1991-2004 Altera Corporation -//Any megafunction design, and related netlist (encrypted or decrypted), -//support information, device programming or simulation file, and any other -//associated documentation or information provided by Altera or a partner -//under Altera's Megafunction Partnership Program may be used only -//to program PLD devices (but not masked PLD devices) from Altera. Any -//other use of such megafunction design, netlist, support information, -//device programming or simulation file, or any other related documentation -//or information is prohibited for any other purpose, including, but not -//limited to modification, reverse engineering, de-compiling, or use with -//any other silicon devices, unless such use is explicitly licensed under -//a separate agreement with Altera or a megafunction partner. Title to the -//intellectual property, including patents, copyrights, trademarks, trade -//secrets, or maskworks, embodied in any such megafunction design, netlist, -//support information, device programming or simulation file, or any other -//related documentation or information provided by Altera or a megafunction -//partner, remains with Altera, the megafunction partner, or their respective -//licensors. No other licenses, including any licenses needed under any third -//party's intellectual property, are provided herein. - -module pll ( - inclk0, - c0); - - input inclk0; - output c0; - -endmodule - |