diff options
Diffstat (limited to 'fpga/usrp1/megacells/add32.cmp')
| -rwxr-xr-x | fpga/usrp1/megacells/add32.cmp | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/fpga/usrp1/megacells/add32.cmp b/fpga/usrp1/megacells/add32.cmp deleted file mode 100755 index 3b120176d..000000000 --- a/fpga/usrp1/megacells/add32.cmp +++ /dev/null @@ -1,29 +0,0 @@ ---Copyright (C) 1991-2003 Altera Corporation ---Any megafunction design, and related netlist (encrypted or decrypted), ---support information, device programming or simulation file, and any other ---associated documentation or information provided by Altera or a partner ---under Altera's Megafunction Partnership Program may be used only ---to program PLD devices (but not masked PLD devices) from Altera. Any ---other use of such megafunction design, netlist, support information, ---device programming or simulation file, or any other related documentation ---or information is prohibited for any other purpose, including, but not ---limited to modification, reverse engineering, de-compiling, or use with ---any other silicon devices, unless such use is explicitly licensed under ---a separate agreement with Altera or a megafunction partner. Title to the ---intellectual property, including patents, copyrights, trademarks, trade ---secrets, or maskworks, embodied in any such megafunction design, netlist, ---support information, device programming or simulation file, or any other ---related documentation or information provided by Altera or a megafunction ---partner, remains with Altera, the megafunction partner, or their respective ---licensors. No other licenses, including any licenses needed under any third ---party's intellectual property, are provided herein. - - -component add32 - PORT - ( - dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -end component; |