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-rw-r--r--fpga/docs/usrp3/sim/running_testbenches.md5
1 files changed, 3 insertions, 2 deletions
diff --git a/fpga/docs/usrp3/sim/running_testbenches.md b/fpga/docs/usrp3/sim/running_testbenches.md
index 2e2068e5e..4afd66fe0 100644
--- a/fpga/docs/usrp3/sim/running_testbenches.md
+++ b/fpga/docs/usrp3/sim/running_testbenches.md
@@ -17,8 +17,9 @@ all supported simulator targets. Currently, the following targets will work:
cleanall: Cleanup everything!
xsim: Run the simulation using the Xilinx Vivado Simulator
xclean: Cleanup Xilinx Vivado Simulator intermediate files
- vsim: Run the simulation using Modelsim
- vclean: Cleanup Modelsim intermediate files
+ vsim: Run the simulation using ModelSim simulator via Vivado
+ modelsim: Runs the simulation using ModelSim without Vivado
+ vclean: Cleanup ModelSim intermediate files
## Using Xilinx Vivado XSim