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Diffstat (limited to 'fpga/docs/usrp3')
| -rw-r--r-- | fpga/docs/usrp3/sim/running_testbenches.md | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/docs/usrp3/sim/running_testbenches.md b/fpga/docs/usrp3/sim/running_testbenches.md index 2b56af86d..136834bc6 100644 --- a/fpga/docs/usrp3/sim/running_testbenches.md +++ b/fpga/docs/usrp3/sim/running_testbenches.md @@ -15,6 +15,7 @@ all supported simulator targets. Currently, the following targets will work: ipclean: Cleanup all IP intermediate files clean: Cleanup all simulator intermediate files cleanall: Cleanup everything! + ip: Generate the IP required for this simulation xsim: Run the simulation using the Xilinx Vivado Simulator xclean: Cleanup Xilinx Vivado Simulator intermediate files vsim: Run the simulation using ModelSim simulator via Vivado |