diff options
Diffstat (limited to 'firmware/microblaze')
| -rw-r--r-- | firmware/microblaze/apps/txrx.c | 56 | ||||
| -rw-r--r-- | firmware/microblaze/lib/db.h | 3 | ||||
| -rw-r--r-- | firmware/microblaze/lib/db_init.c | 12 |
3 files changed, 65 insertions, 6 deletions
diff --git a/firmware/microblaze/apps/txrx.c b/firmware/microblaze/apps/txrx.c index 5f4c595f8..abea1bf0c 100644 --- a/firmware/microblaze/apps/txrx.c +++ b/firmware/microblaze/apps/txrx.c @@ -156,6 +156,9 @@ void handle_udp_data_packet( _is_data = true; } +#define OTW_GPIO_BANK_TO_NUM(bank) \ + (((bank) == USRP2_GPIO_BANK_RX)? (GPIO_RX_BANK) : (GPIO_TX_BANK)) + void handle_udp_ctrl_packet( struct socket_address src, struct socket_address dst, unsigned char *payload, int payload_len @@ -176,6 +179,9 @@ void handle_udp_ctrl_packet( //handle the data based on the id switch(ctrl_data_in->id){ + /******************************************************************* + * Addressing + ******************************************************************/ case USRP2_CTRL_ID_GIVE_ME_YOUR_IP_ADDR_BRO: ctrl_data_out.id = USRP2_CTRL_ID_THIS_IS_MY_IP_ADDR_DUDE; struct ip_addr ip_addr = get_my_ip_addr(); @@ -194,6 +200,9 @@ void handle_udp_ctrl_packet( ctrl_data_out.data.dboard_ids.rx_id = read_dboard_eeprom(I2C_ADDR_RX_A); break; + /******************************************************************* + * Clock Config + ******************************************************************/ case USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO: //TODO handle MC_PROVIDE_CLK_TO_MIMO when we do MIMO setup ctrl_data_out.id = USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE; @@ -232,6 +241,53 @@ void handle_udp_ctrl_packet( break; + /******************************************************************* + * GPIO + ******************************************************************/ + case USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO: + hal_gpio_set_ddr( + OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.gpio_config.bank), + ctrl_data_in->data.gpio_config.value, + ctrl_data_in->data.gpio_config.mask + ); + ctrl_data_out.id = USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE; + break; + + case USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO: + hal_gpio_write( + OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.gpio_config.bank), + ctrl_data_in->data.gpio_config.value, + ctrl_data_in->data.gpio_config.mask + ); + ctrl_data_out.id = USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE; + break; + + case USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO: + ctrl_data_out.data.gpio_config.value = hal_gpio_read( + OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.gpio_config.bank) + ); + ctrl_data_out.id = USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE; + break; + + case USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO:{ + //setup the atr registers for this bank + int bank = OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.atr_config.bank); + set_atr_regs( + bank, + ctrl_data_in->data.atr_config.rx_value, + ctrl_data_in->data.atr_config.tx_value + ); + + //setup the sels based on the atr config mask + int mask = ctrl_data_in->data.atr_config.mask; + for (int i = 0; i < 16; i++){ + // set to either GPIO_SEL_SW or GPIO_SEL_ATR + hal_gpio_set_sel(bank, i, (mask & (1 << i)) ? 'a' : 's'); + } + ctrl_data_out.id = USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE; + } + break; + default: ctrl_data_out.id = USRP2_CTRL_ID_HUH_WHAT; diff --git a/firmware/microblaze/lib/db.h b/firmware/microblaze/lib/db.h index 9cd0b379a..5153822c6 100644 --- a/firmware/microblaze/lib/db.h +++ b/firmware/microblaze/lib/db.h @@ -103,4 +103,7 @@ bool db_set_gain(struct db_base *db, u2_fxpt_gain_t gain); +void +set_atr_regs(int bank, int atr_rxval, int atr_txval); + #endif /* INCLUDED_DB_H */ diff --git a/firmware/microblaze/lib/db_init.c b/firmware/microblaze/lib/db_init.c index 4d6081cbc..4a0b49ada 100644 --- a/firmware/microblaze/lib/db_init.c +++ b/firmware/microblaze/lib/db_init.c @@ -105,17 +105,17 @@ lookup_dboard(int i2c_addr, struct db_base *default_db, char *msg) } void -set_atr_regs(int bank, struct db_base *db) +set_atr_regs(int bank, int atr_rxval, int atr_txval) { uint32_t val[4]; int shift; int mask; int i; - val[ATR_IDLE] = 0;//db->atr_rxval; - val[ATR_RX] = 0;//db->atr_rxval; - val[ATR_TX] = 0;//db->atr_txval; - val[ATR_FULL] = 0;//db->atr_txval; + val[ATR_IDLE] = atr_rxval; + val[ATR_RX] = atr_rxval; + val[ATR_TX] = atr_txval; + val[ATR_FULL] = atr_txval; if (bank == GPIO_TX_BANK){ mask = 0xffff0000; @@ -139,7 +139,7 @@ set_gpio_mode(int bank, struct db_base *db) int i; hal_gpio_set_ddr(bank, /*db->output_enables*/0, 0xffff); - set_atr_regs(bank, db); + //set_atr_regs(bank, db); for (i = 0; i < 16; i++){ if (/*db->used_pins*/0 & (1 << i)){ |