diff options
Diffstat (limited to 'firmware/microblaze/usrp2p')
| -rw-r--r-- | firmware/microblaze/usrp2p/.gitignore | 9 | ||||
| -rw-r--r-- | firmware/microblaze/usrp2p/CMakeLists.txt | 48 | ||||
| -rw-r--r-- | firmware/microblaze/usrp2p/bootloader/.gitignore | 11 | ||||
| -rw-r--r-- | firmware/microblaze/usrp2p/bootloader/CMakeLists.txt | 39 | ||||
| -rw-r--r-- | firmware/microblaze/usrp2p/bootloader/init_bootloader.c | 22 | ||||
| -rw-r--r-- | firmware/microblaze/usrp2p/bootloader_utils.c | 25 | ||||
| -rw-r--r-- | firmware/microblaze/usrp2p/bootloader_utils.h | 6 | ||||
| -rw-r--r-- | firmware/microblaze/usrp2p/ethernet.c | 95 | ||||
| -rw-r--r-- | firmware/microblaze/usrp2p/memory_map.h | 187 | ||||
| -rw-r--r-- | firmware/microblaze/usrp2p/spi_flash_read.c | 6 |
10 files changed, 149 insertions, 299 deletions
diff --git a/firmware/microblaze/usrp2p/.gitignore b/firmware/microblaze/usrp2p/.gitignore deleted file mode 100644 index 18f715618..000000000 --- a/firmware/microblaze/usrp2p/.gitignore +++ /dev/null @@ -1,9 +0,0 @@ -/Makefile -/Makefile.in -/*.a -/*.bin -/*.dump -/*.ihx -/*.elf -/*.rom -/*.map diff --git a/firmware/microblaze/usrp2p/CMakeLists.txt b/firmware/microblaze/usrp2p/CMakeLists.txt new file mode 100644 index 000000000..41ef8f1dd --- /dev/null +++ b/firmware/microblaze/usrp2p/CMakeLists.txt @@ -0,0 +1,48 @@ +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +######################################################################## +INCLUDE(${CMAKE_SOURCE_DIR}/lib/CMakeLists.txt) +INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR}) + +ADD_DEFINITIONS(-DUSRP2P) + +ADD_LIBRARY(libusrp2pfw STATIC + ${COMMON_SRCS} + spif.c + spi_flash.c + spi_flash_read.c + bootloader_utils.c + ethernet.c + xilinx_s3_icap.c + udp_fw_update.c +) + +ADD_SUBDIRECTORY(bootloader) + +######################################################################## +ADD_EXECUTABLE(usrp2p_txrx_uhd.elf ${CMAKE_SOURCE_DIR}/apps/txrx_uhd.c) +TARGET_LINK_LIBRARIES(usrp2p_txrx_uhd.elf libusrp2pfw) +GEN_OUTPUTS(usrp2p_txrx_uhd.elf) + +ADD_EXECUTABLE(usrp2p_blinkenlights.elf ${CMAKE_SOURCE_DIR}/apps/blinkenlights.c) +TARGET_LINK_LIBRARIES(usrp2p_blinkenlights.elf libusrp2pfw) +GEN_OUTPUTS(usrp2p_blinkenlights.elf) + +ADD_EXECUTABLE(usrp2p_uart_flash_loader.elf ${CMAKE_SOURCE_DIR}/apps/uart_flash_loader.c) +TARGET_LINK_LIBRARIES(usrp2p_uart_flash_loader.elf libusrp2pfw) +GEN_OUTPUTS(usrp2p_uart_flash_loader.elf) diff --git a/firmware/microblaze/usrp2p/bootloader/.gitignore b/firmware/microblaze/usrp2p/bootloader/.gitignore deleted file mode 100644 index 17b0f82f3..000000000 --- a/firmware/microblaze/usrp2p/bootloader/.gitignore +++ /dev/null @@ -1,11 +0,0 @@ -/*.ihx -/*.rmi -/*_rom -/*.elf -/*.bin -/*.dump -/*.log -/*.rom -/*.map -/Makefile -/Makefile.in diff --git a/firmware/microblaze/usrp2p/bootloader/CMakeLists.txt b/firmware/microblaze/usrp2p/bootloader/CMakeLists.txt new file mode 100644 index 000000000..41c86cc9a --- /dev/null +++ b/firmware/microblaze/usrp2p/bootloader/CMakeLists.txt @@ -0,0 +1,39 @@ +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +######################################################################## +INCLUDE(FindPythonInterp) + +MACRO(GEN_RMI target) + GET_FILENAME_COMPONENT(name ${target} NAME_WE) + #command to create a rmi from elf + ADD_CUSTOM_COMMAND( + OUTPUT ${name}.rmi DEPENDS ${name}.bin + COMMAND ${PYTHON_EXECUTABLE} + ARGS ${CMAKE_SOURCE_DIR}/bin/bin_to_ram_macro_init.py ${name}.bin ${name}.rmi + ) + #add a top level target for output files + ADD_CUSTOM_TARGET( + ${name}_rmi ALL DEPENDS ${name}.rmi + ) +ENDMACRO(GEN_RMI) + +######################################################################## +ADD_EXECUTABLE(init_bootloader.elf init_bootloader.c) +TARGET_LINK_LIBRARIES(init_bootloader.elf libusrp2pfw) +GEN_OUTPUTS(init_bootloader.elf) +GEN_RMI(init_bootloader.bin) diff --git a/firmware/microblaze/usrp2p/bootloader/init_bootloader.c b/firmware/microblaze/usrp2p/bootloader/init_bootloader.c index 1d9d681d7..cfa80ffea 100644 --- a/firmware/microblaze/usrp2p/bootloader/init_bootloader.c +++ b/firmware/microblaze/usrp2p/bootloader/init_bootloader.c @@ -18,7 +18,7 @@ #include <i2c.h> #include "usrp2/fw_common.h" -void pic_interrupt_handler() __attribute__ ((interrupt_handler)); +//void pic_interrupt_handler() __attribute__ ((interrupt_handler)); void pic_interrupt_handler() { @@ -42,7 +42,7 @@ void load_ihex(void) { //simple IHEX parser to load proper records into RAM. loa } else if(ihex_record.type == 1) { //end of record puts("OK"); //load main firmware - start_program(RAM_BASE); + start_program(); puts("ERROR: main image returned! Back in IHEX load mode."); } else puts("NOK"); //RAM loads do not support extended segment address records (04) -- upper 16 bits are always "0". } else puts("NOK"); @@ -56,12 +56,12 @@ void delay(uint32_t t) { int main(int argc, char *argv[]) { hal_disable_ints(); // In case we got here via jmp 0x0 output_regs->leds = 0xFF; - delay(500000); + delay(5000); output_regs->leds = 0x00; hal_uart_init(); spif_init(); i2c_init(); //for EEPROM - puts("USRP2+ bootloader\n"); + puts("USRP2+ bootloader super ultra ZPU edition\n"); bool production_image = find_safe_booted_flag(); set_safe_booted_flag(0); //haven't booted yet @@ -71,7 +71,7 @@ int main(int argc, char *argv[]) { if(is_valid_fw_image(SAFE_FW_IMAGE_LOCATION_ADDR)) { set_safe_booted_flag(1); //let the firmware know it's the safe image spi_flash_read(SAFE_FW_IMAGE_LOCATION_ADDR, FW_IMAGE_SIZE_BYTES, (void *)RAM_BASE); - start_program(RAM_BASE); + start_program(); puts("ERROR: return from main program! This should never happen!"); icap_reload_fpga(SAFE_FPGA_IMAGE_LOCATION_ADDR); } else { @@ -85,7 +85,7 @@ int main(int argc, char *argv[]) { if(is_valid_fpga_image(PROD_FPGA_IMAGE_LOCATION_ADDR)) { puts("Valid production FPGA image found. Attempting to boot."); set_safe_booted_flag(1); - delay(30000); //so serial output can finish + delay(300); //so serial output can finish icap_reload_fpga(PROD_FPGA_IMAGE_LOCATION_ADDR); } puts("No valid production FPGA image found.\nAttempting to load production firmware..."); @@ -93,17 +93,23 @@ int main(int argc, char *argv[]) { if(is_valid_fw_image(PROD_FW_IMAGE_LOCATION_ADDR)) { puts("Valid production firmware found. Loading..."); spi_flash_read(PROD_FW_IMAGE_LOCATION_ADDR, FW_IMAGE_SIZE_BYTES, (void *)RAM_BASE); - start_program(RAM_BASE); + puts("Finished loading. Starting image."); + delay(300); + start_program(); puts("ERROR: Return from main program! This should never happen!"); //if this happens, though, the safest thing to do is reboot the whole FPGA and start over. + delay(300); icap_reload_fpga(SAFE_FPGA_IMAGE_LOCATION_ADDR); return 1; } puts("No valid production firmware found. Trying safe firmware..."); if(is_valid_fw_image(SAFE_FW_IMAGE_LOCATION_ADDR)) { spi_flash_read(SAFE_FW_IMAGE_LOCATION_ADDR, FW_IMAGE_SIZE_BYTES, (void *)RAM_BASE); - start_program(RAM_BASE); + puts("Finished loading. Starting image."); + delay(300); + start_program(); puts("ERROR: return from main program! This should never happen!"); + delay(300); icap_reload_fpga(SAFE_FPGA_IMAGE_LOCATION_ADDR); return 1; } diff --git a/firmware/microblaze/usrp2p/bootloader_utils.c b/firmware/microblaze/usrp2p/bootloader_utils.c index fadd225bb..379c5f957 100644 --- a/firmware/microblaze/usrp2p/bootloader_utils.c +++ b/firmware/microblaze/usrp2p/bootloader_utils.c @@ -10,30 +10,39 @@ #include <string.h> #include <bootloader_utils.h> #include <spi_flash.h> +#include <memory_map.h> +#include <nonstdio.h> int is_valid_fpga_image(uint32_t addr) { +// printf("is_valid_fpga_image(): starting with addr=%x...\n", addr); uint8_t imgbuf[64]; spi_flash_read(addr, 64, imgbuf); //we're just looking for leading 0xFF padding, followed by the sync bytes 0xAA 0x99 - int i = 0; - for(i; i<63; i++) { + for(size_t i = 0; i<63; i++) { if(imgbuf[i] == 0xFF) continue; - if(imgbuf[i] == 0xAA && imgbuf[i+1] == 0x99) return 1; + if(imgbuf[i] == 0xAA && imgbuf[i+1] == 0x99) { + //printf("is_valid_fpga_image(): found valid FPGA image\n"); + return 1; + } } return 0; } int is_valid_fw_image(uint32_t addr) { - static const uint8_t fwheader[] = {0xB0, 0x00, 0x00, 0x00, 0xB8, 0x08}; //just lookin for a jump to anywhere located at the reset vector + static const uint8_t fwheader[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x80, 0x70}; //just lookin for a jump to anywhere located at the reset vector + //printf("is_valid_fw_image(): starting with addr=%x...\n", addr); uint8_t buf[12]; spi_flash_read(addr, 6, buf); + //printf("is_valid_fw_image(): read "); + //for(int i = 0; i < 5; i++) printf("%x ", buf[i]); + //printf("\n"); return memcmp(buf, fwheader, 6) == 0; } -void start_program(uint32_t addr) +void start_program(void) { - memcpy(0x00000000, addr+0x00000000, 36); //copy the whole vector table, with the reset vector, into boot RAM - typedef void (*fptr_t)(void); - (*(fptr_t) 0x00000000)(); // most likely no return + //ignoring the addr now + //all this does is tap that register + *((volatile uint32_t *) SR_ADDR_BLDRDONE) = 1; } diff --git a/firmware/microblaze/usrp2p/bootloader_utils.h b/firmware/microblaze/usrp2p/bootloader_utils.h index f597c0113..0f49ae6cd 100644 --- a/firmware/microblaze/usrp2p/bootloader_utils.h +++ b/firmware/microblaze/usrp2p/bootloader_utils.h @@ -9,8 +9,8 @@ //we're working in bytes and byte addresses so we can run the same code with Flash chips of different sector sizes. //it's really 1463736, but rounded up to 1.5MB #define FPGA_IMAGE_SIZE_BYTES 1572864 -//instead of 32K, we write 31K because we're using the top 1K for stack space! -#define FW_IMAGE_SIZE_BYTES 31744 +//16K +#define FW_IMAGE_SIZE_BYTES 0x3fff #define SAFE_FPGA_IMAGE_LOCATION_ADDR 0x00000000 #define SAFE_FW_IMAGE_LOCATION_ADDR 0x003F0000 @@ -19,4 +19,4 @@ int is_valid_fpga_image(uint32_t addr); int is_valid_fw_image(uint32_t addr); -void start_program(uint32_t addr); +void start_program(void); diff --git a/firmware/microblaze/usrp2p/ethernet.c b/firmware/microblaze/usrp2p/ethernet.c index 36d6a17ca..03891f959 100644 --- a/firmware/microblaze/usrp2p/ethernet.c +++ b/firmware/microblaze/usrp2p/ethernet.c @@ -279,101 +279,6 @@ ethernet_init(void) eth_mac_miim_write(PHY_CTRL, t | MII_CR_RESTART_AUTO_NEG); } -static bool -unprogrammed(const void *t, size_t len) -{ - int i; - uint8_t *p = (uint8_t *)t; - bool all_zeros = true; - bool all_ones = true; - for (i = 0; i < len; i++){ - all_zeros &= p[i] == 0x00; - all_ones &= p[i] == 0xff; - } - return all_ones | all_zeros; -} - -//////////////////// MAC Addr Stuff /////////////////////// -/* -static int8_t src_mac_addr_initialized = false; -static eth_mac_addr_t src_mac_addr = {{ - 0x00, 0x50, 0xC2, 0x85, 0x3f, 0xff - }}; - -const eth_mac_addr_t * -ethernet_mac_addr(void) -{ - if (!src_mac_addr_initialized){ // fetch from eeprom - src_mac_addr_initialized = true; - - // if we're simulating, don't read the EEPROM model, it's REALLY slow - if (hwconfig_simulation_p()) - return &src_mac_addr; - - eth_mac_addr_t tmp; - bool ok = eeprom_read(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_MAC_ADDR, &tmp, sizeof(tmp)); - if (!ok || unprogrammed(&tmp, sizeof(tmp))){ - // use the default - } - else - src_mac_addr = tmp; - } - - return &src_mac_addr; -} - -bool -ethernet_set_mac_addr(const eth_mac_addr_t *t) -{ - bool ok = eeprom_write(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_MAC_ADDR, t, sizeof(eth_mac_addr_t)); - if (ok){ - src_mac_addr = *t; - src_mac_addr_initialized = true; - //eth_mac_set_addr(t); //this breaks the link - } - - return ok; -} - -//////////////////// IP Addr Stuff /////////////////////// - -static int8_t src_ip_addr_initialized = false; -static struct ip_addr src_ip_addr = { - (192 << 24 | 168 << 16 | 10 << 8 | 2 << 0) -}; - - -const struct ip_addr *get_ip_addr(void) -{ - if (!src_ip_addr_initialized){ // fetch from eeprom - src_ip_addr_initialized = true; - - // if we're simulating, don't read the EEPROM model, it's REALLY slow - if (hwconfig_simulation_p()) - return &src_ip_addr; - - struct ip_addr tmp; - bool ok = eeprom_read(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_IP_ADDR, &tmp, sizeof(tmp)); - if (!ok || unprogrammed(&tmp, sizeof(tmp))){ - // use the default - } - else - src_ip_addr = tmp; - } - - return &src_ip_addr; -} - -bool set_ip_addr(const struct ip_addr *t){ - bool ok = eeprom_write(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_IP_ADDR, t, sizeof(struct ip_addr)); - if (ok){ - src_ip_addr = *t; - src_ip_addr_initialized = true; - } - - return ok; -} -*/ int ethernet_check_errors(void) { diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h index db47d0b5f..6f5c577e6 100644 --- a/firmware/microblaze/usrp2p/memory_map.h +++ b/firmware/microblaze/usrp2p/memory_map.h @@ -16,38 +16,6 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -/* Overall Memory Map - * 0000-FFFF 64K RAM space - * - * 0000-1FFF 8K Boot RAM - * 2000-5FFF 16K Buffer pool - * 6000-7FFF 8K Peripherals - * 8000-FFFF 32K Main System RAM - - -From u2plus_core.v: -wb_1master #(.decode_w(8), -.s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM -.s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000), // 16K-32K, Buffer Pool -.s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111), // SPI 0x3000 -.s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111), // I2C 0x3100 -.s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111), // GPIO 0x3200 -.s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111), // Readback 0x3300 -.s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111), // Ethernet MAC 0x3400 -.s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000), // 8-12K, Settings Bus (only uses 1K) 0x2000-0x2FFF -.s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111), // PIC 0x3500 -.s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111), // Unused 0x3600 -.sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111), // UART 0x3700 -.sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111), // ATR 0x3800 -.sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111), // Unused 0x3900 -.sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111), // ICAP 0x3A00 -.se_addr(8'b0011_1011),.se_mask(8'b1111_1111), // SPI Flash 0x3B00 -.sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000), // 32-64K, Main RAM 0x8000-0xFFFF - .dw(dw),.aw(aw),.sw(sw)) wb_1master - - */ - - #ifndef INCLUDED_MEMORY_MAP_H #define INCLUDED_MEMORY_MAP_H @@ -78,9 +46,7 @@ wb_1master #(.decode_w(8), #define BUFFER_POOL_RAM_BASE 0x4000 -#define NBUFFERS 8 #define BP_NLINES 0x0200 // number of 32-bit lines in a buffer -#define BP_LAST_LINE (BP_NLINES - 1) // last line in a buffer #define buffer_pool_ram \ ((uint32_t *) BUFFER_POOL_RAM_BASE) @@ -90,7 +56,7 @@ wb_1master #(.decode_w(8), ///////////////////////////////////////////////////// // SPI Core, Slave 2. See core docs for more info -#define SPI_BASE 0x3000 // Base address (16-bit) is base peripheral addr +#define SPI_BASE 0x6000 // Base address (16-bit) is base peripheral addr typedef struct { volatile uint32_t txrx0; @@ -129,7 +95,7 @@ typedef struct { // I2C, Slave 3 // See Wishbone I2C-Master Core Specification. -#define I2C_BASE 0x3100 +#define I2C_BASE 0x6100 typedef struct { volatile uint32_t prescaler_lo; // r/w @@ -171,7 +137,7 @@ typedef struct { // // These go to the daughterboard i/o pins -#define GPIO_BASE 0x3200 +#define GPIO_BASE 0x6200 typedef struct { volatile uint32_t io; // tx data in high 16, rx in low 16 @@ -195,11 +161,11 @@ typedef struct { // The status registers are in Slave 5, Buffer Pool Status. // The control register is in Slave 7, Settings Bus. -#define BUFFER_POOL_STATUS_BASE 0x3300 +#define BUFFER_POOL_STATUS_BASE 0x6300 typedef struct { - volatile uint32_t last_line[NBUFFERS]; // last line xfer'd in buffer - volatile uint32_t status; // error and done flags + volatile uint32_t _padding[8]; + volatile uint32_t status; volatile uint32_t hw_config; // see below volatile uint32_t dummy[3]; volatile uint32_t irqs; @@ -211,74 +177,6 @@ typedef struct { #define BUTTON_PUSHED ((buffer_pool_status->irqs & PIC_BUTTON) ? 0 : 1) -/* - * Buffer n's xfer is done. - * Clear this bit by issuing bp_clear_buf(n) - */ -#define BPS_DONE(n) (0x00000001 << (n)) -#define BPS_DONE_0 BPS_DONE(0) -#define BPS_DONE_1 BPS_DONE(1) -#define BPS_DONE_2 BPS_DONE(2) -#define BPS_DONE_3 BPS_DONE(3) -#define BPS_DONE_4 BPS_DONE(4) -#define BPS_DONE_5 BPS_DONE(5) -#define BPS_DONE_6 BPS_DONE(6) -#define BPS_DONE_7 BPS_DONE(7) - -/* - * Buffer n's xfer had an error. - * Clear this bit by issuing bp_clear_buf(n) - */ -#define BPS_ERROR(n) (0x00000100 << (n)) -#define BPS_ERROR_0 BPS_ERROR(0) -#define BPS_ERROR_1 BPS_ERROR(1) -#define BPS_ERROR_2 BPS_ERROR(2) -#define BPS_ERROR_3 BPS_ERROR(3) -#define BPS_ERROR_4 BPS_ERROR(4) -#define BPS_ERROR_5 BPS_ERROR(5) -#define BPS_ERROR_6 BPS_ERROR(6) -#define BPS_ERROR_7 BPS_ERROR(7) - -/* - * Buffer n is idle. A buffer is idle if it's not - * DONE, ERROR, or processing a transaction. If it's - * IDLE, it's safe to start a new transaction. - * - * Clear this bit by starting a xfer with - * bp_send_from_buf or bp_receive_to_buf. - */ -#define BPS_IDLE(n) (0x00010000 << (n)) -#define BPS_IDLE_0 BPS_IDLE(0) -#define BPS_IDLE_1 BPS_IDLE(1) -#define BPS_IDLE_2 BPS_IDLE(2) -#define BPS_IDLE_3 BPS_IDLE(3) -#define BPS_IDLE_4 BPS_IDLE(4) -#define BPS_IDLE_5 BPS_IDLE(5) -#define BPS_IDLE_6 BPS_IDLE(6) -#define BPS_IDLE_7 BPS_IDLE(7) - -/* - * Buffer n has a "slow path" packet in it. - * This bit is orthogonal to the bits above and indicates that - * the FPGA ethernet rx protocol engine has identified this packet - * as one requiring firmware intervention. - */ -#define BPS_SLOWPATH(n) (0x01000000 << (n)) -#define BPS_SLOWPATH_0 BPS_SLOWPATH(0) -#define BPS_SLOWPATH_1 BPS_SLOWPATH(1) -#define BPS_SLOWPATH_2 BPS_SLOWPATH(2) -#define BPS_SLOWPATH_3 BPS_SLOWPATH(3) -#define BPS_SLOWPATH_4 BPS_SLOWPATH(4) -#define BPS_SLOWPATH_5 BPS_SLOWPATH(5) -#define BPS_SLOWPATH_6 BPS_SLOWPATH(6) -#define BPS_SLOWPATH_7 BPS_SLOWPATH(7) - - -#define BPS_DONE_ALL 0x000000ff // mask of all dones -#define BPS_ERROR_ALL 0x0000ff00 // mask of all errors -#define BPS_IDLE_ALL 0x00ff0000 // mask of all idles -#define BPS_SLOWPATH_ALL 0xff000000 // mask of all slowpaths - // The hw_config register #define HWC_SIMULATION 0x80000000 @@ -306,7 +204,7 @@ hwconfig_wishbone_divisor(void) /////////////////////////////////////////////////// // Ethernet Core, Slave 6 -#define ETH_BASE 0x3400 +#define ETH_BASE 0x6400 #include "eth_mac_regs.h" @@ -319,11 +217,7 @@ hwconfig_wishbone_divisor(void) // 1KB of address space (== 256 32-bit write-only regs) -#define MISC_OUTPUT_BASE 0x2000 -#define TX_PROTOCOL_ENGINE_BASE 0x2080 -#define RX_PROTOCOL_ENGINE_BASE 0x20C0 -#define BUFFER_POOL_CTRL_BASE 0x2100 -#define LAST_SETTING_REG 0x23FC // last valid setting register +#define MISC_OUTPUT_BASE 0x5000 #define SR_MISC 0 #define SR_TX_PROT_ENG 32 @@ -340,53 +234,20 @@ hwconfig_wishbone_divisor(void) #define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) +#define SR_ADDR_BLDRDONE _SR_ADDR(5) + // --- buffer pool control regs --- typedef struct { - volatile uint32_t ctrl; + volatile uint32_t misc_ctrl; + volatile uint32_t ip_addr; + volatile uint32_t ctrl_ports; //ctrl (low 16) other (high 16) + volatile uint32_t data_ports; //dsp0 (low 16) dsp1 (high 16) + volatile uint32_t cpu_out_ctrl; + volatile uint32_t cpu_inp_ctrl; } buffer_pool_ctrl_t; -// buffer pool ports - -#define PORT_SERDES 0 // serial/deserializer -#define PORT_DSP 1 // DSP tx or rx pipeline -#define PORT_ETH 2 // ethernet tx or rx -#define PORT_RAM 3 // RAM tx or rx - -// the buffer pool ctrl register fields - -#define BPC_BUFFER(n) (((n) & 0xf) << 28) -#define BPC_BUFFER_MASK BPC_BUFFER(~0) -#define BPC_BUFFER_0 BPC_BUFFER(0) -#define BPC_BUFFER_1 BPC_BUFFER(1) -#define BPC_BUFFER_2 BPC_BUFFER(2) -#define BPC_BUFFER_3 BPC_BUFFER(3) -#define BPC_BUFFER_4 BPC_BUFFER(4) -#define BPC_BUFFER_5 BPC_BUFFER(5) -#define BPC_BUFFER_6 BPC_BUFFER(6) -#define BPC_BUFFER_7 BPC_BUFFER(7) -#define BPC_BUFFER_NIL BPC_BUFFER(0x8) // disable - -#define BPC_PORT(n) (((n) & 0x7) << 25) -#define BPC_PORT_MASK BPC_PORT(~0) -#define BPC_PORT_SERDES BPC_PORT(PORT_SERDES) -#define BPC_PORT_DSP BPC_PORT(PORT_DSP) -#define BPC_PORT_ETH BPC_PORT(PORT_ETH) -#define BPC_PORT_RAM BPC_PORT(PORT_RAM) -#define BPC_PORT_NIL BPC_PORT(0x4) // disable - -#define BPC_CLR (1 << 24) // mutually excl commands -#define BPC_READ (1 << 23) -#define BPC_WRITE (1 << 22) - -#define BPC_STEP(step) (((step) & 0xf) << 18) -#define BPC_STEP_MASK BPC_STEP(~0) -#define BPC_LAST_LINE(line) (((line) & 0x1ff) << 9) -#define BPC_LAST_LINE_MASK BPC_LAST_LINE(~0) -#define BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0) -#define BPC_FIRST_LINE_MASK BPC_FIRST_LINE(~0) - -#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE) +#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) _SR_ADDR(SR_BUFFER_POOL_CTRL)) // --- misc outputs --- @@ -689,7 +550,7 @@ typedef struct { volatile uint32_t seqno; // Write to init seqno. It autoincs on match } tx_proto_engine_regs_t; -#define tx_proto_engine ((tx_proto_engine_regs_t *) TX_PROTOCOL_ENGINE_BASE) +#define tx_proto_engine ((tx_proto_engine_regs_t *) _SR_ADDR(SR_TX_PROT_ENG)) /* * --- ethernet rx protocol engine regs (write only) --- @@ -716,14 +577,14 @@ typedef struct { volatile uint32_t ethertype_pad; // ethertype in high 16-bits } rx_proto_engine_regs_t; -#define rx_proto_engine ((rx_proto_engine_regs_t *) RX_PROTOCOL_ENGINE_BASE) +#define rx_proto_engine ((rx_proto_engine_regs_t *) _SR_ADDR(SR_RX_PROT_ENG)) /////////////////////////////////////////////////// // Simple Programmable Interrupt Controller, Slave 8 -#define PIC_BASE 0x3500 +#define PIC_BASE 0x6500 // Interrupt request lines // Bit numbers (LSB == 0) that correpond to interrupts into PIC @@ -783,7 +644,7 @@ typedef struct { /////////////////////////////////////////////////// // UART, Slave 10 -#define UART_BASE 0x3700 +#define UART_BASE 0x6700 typedef struct { // All elements are 8 bits except for clkdiv (16), but we use uint32 to make @@ -801,7 +662,7 @@ typedef struct { /////////////////////////////////////////////////// // ATR Controller, Slave 11 -#define ATR_BASE 0x3800 +#define ATR_BASE 0x6800 typedef struct { volatile uint32_t v[16]; @@ -820,7 +681,7 @@ typedef struct { /////////////////////////////////////////////////// // ICAP, Slave 13 -#define ICAP_BASE 0x3A00 +#define ICAP_BASE 0x6A00 typedef struct { uint32_t icap; //only the lower 8 bits matter } icap_regs_t; @@ -832,7 +693,7 @@ typedef struct { // Control register definitions are the same as SPI, so use SPI_CTRL_ASS, etc. // Peripheral mask not needed since bus is dedicated (CE held low) -#define SPIF_BASE 0x3B00 +#define SPIF_BASE 0x6B00 typedef struct { volatile uint32_t txrx0; volatile uint32_t txrx1; diff --git a/firmware/microblaze/usrp2p/spi_flash_read.c b/firmware/microblaze/usrp2p/spi_flash_read.c index 4682c5fe6..36c326e96 100644 --- a/firmware/microblaze/usrp2p/spi_flash_read.c +++ b/firmware/microblaze/usrp2p/spi_flash_read.c @@ -19,6 +19,7 @@ #include "spi_flash_private.h" #include <stdlib.h> // abort +#include <nonstdio.h> static size_t _spi_flash_log2_memory_size; @@ -100,7 +101,8 @@ spi_flash_read(uint32_t flash_addr, size_t nbytes, void *buf) */ unsigned char *dst = (unsigned char *) buf; size_t m; - for (size_t n = 0; n < nbytes; n += m, dst += m){ + for (size_t n = 0; n < nbytes; n += m){ + spif_regs->ctrl = FLAGS | LEN(16 * 8); // xfer 16 bytes spif_regs->ctrl = FLAGS | LEN(16 * 8) | SPI_CTRL_GO_BSY; spif_wait(); @@ -113,7 +115,7 @@ spi_flash_read(uint32_t flash_addr, size_t nbytes, void *buf) unsigned char *src = (unsigned char *) &w[0]; m = min(nbytes - n, 16); for (size_t i = 0; i < m; i++) - dst[i] = src[i]; + *(dst++) = src[i]; } spif_regs->ss = 0; // deassert chip select } |