diff options
Diffstat (limited to 'firmware/microblaze/usrp2p/memory_map.h')
| -rw-r--r-- | firmware/microblaze/usrp2p/memory_map.h | 187 |
1 files changed, 24 insertions, 163 deletions
diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/microblaze/usrp2p/memory_map.h index 3b2dc0057..2b5ae57be 100644 --- a/firmware/microblaze/usrp2p/memory_map.h +++ b/firmware/microblaze/usrp2p/memory_map.h @@ -16,38 +16,6 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -/* Overall Memory Map - * 0000-FFFF 64K RAM space - * - * 0000-1FFF 8K Boot RAM - * 2000-5FFF 16K Buffer pool - * 6000-7FFF 8K Peripherals - * 8000-FFFF 32K Main System RAM - - -From u2plus_core.v: -wb_1master #(.decode_w(8), -.s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM -.s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000), // 16K-32K, Buffer Pool -.s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111), // SPI 0x3000 -.s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111), // I2C 0x3100 -.s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111), // GPIO 0x3200 -.s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111), // Readback 0x3300 -.s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111), // Ethernet MAC 0x3400 -.s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000), // 8-12K, Settings Bus (only uses 1K) 0x2000-0x2FFF -.s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111), // PIC 0x3500 -.s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111), // Unused 0x3600 -.sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111), // UART 0x3700 -.sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111), // ATR 0x3800 -.sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111), // Unused 0x3900 -.sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111), // ICAP 0x3A00 -.se_addr(8'b0011_1011),.se_mask(8'b1111_1111), // SPI Flash 0x3B00 -.sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000), // 32-64K, Main RAM 0x8000-0xFFFF - .dw(dw),.aw(aw),.sw(sw)) wb_1master - - */ - - #ifndef INCLUDED_MEMORY_MAP_H #define INCLUDED_MEMORY_MAP_H @@ -78,9 +46,7 @@ wb_1master #(.decode_w(8), #define BUFFER_POOL_RAM_BASE 0x4000 -#define NBUFFERS 8 #define BP_NLINES 0x0200 // number of 32-bit lines in a buffer -#define BP_LAST_LINE (BP_NLINES - 1) // last line in a buffer #define buffer_pool_ram \ ((uint32_t *) BUFFER_POOL_RAM_BASE) @@ -90,7 +56,7 @@ wb_1master #(.decode_w(8), ///////////////////////////////////////////////////// // SPI Core, Slave 2. See core docs for more info -#define SPI_BASE 0x3000 // Base address (16-bit) is base peripheral addr +#define SPI_BASE 0x6000 // Base address (16-bit) is base peripheral addr typedef struct { volatile uint32_t txrx0; @@ -129,7 +95,7 @@ typedef struct { // I2C, Slave 3 // See Wishbone I2C-Master Core Specification. -#define I2C_BASE 0x3100 +#define I2C_BASE 0x6100 typedef struct { volatile uint32_t prescaler_lo; // r/w @@ -171,7 +137,7 @@ typedef struct { // // These go to the daughterboard i/o pins -#define GPIO_BASE 0x3200 +#define GPIO_BASE 0x6200 typedef struct { volatile uint32_t io; // tx data in high 16, rx in low 16 @@ -195,11 +161,11 @@ typedef struct { // The status registers are in Slave 5, Buffer Pool Status. // The control register is in Slave 7, Settings Bus. -#define BUFFER_POOL_STATUS_BASE 0x3300 +#define BUFFER_POOL_STATUS_BASE 0x6300 typedef struct { - volatile uint32_t last_line[NBUFFERS]; // last line xfer'd in buffer - volatile uint32_t status; // error and done flags + volatile uint32_t _padding[8]; + volatile uint32_t status; volatile uint32_t hw_config; // see below volatile uint32_t dummy[3]; volatile uint32_t irqs; @@ -211,74 +177,6 @@ typedef struct { #define BUTTON_PUSHED ((buffer_pool_status->irqs & PIC_BUTTON) ? 0 : 1) -/* - * Buffer n's xfer is done. - * Clear this bit by issuing bp_clear_buf(n) - */ -#define BPS_DONE(n) (0x00000001 << (n)) -#define BPS_DONE_0 BPS_DONE(0) -#define BPS_DONE_1 BPS_DONE(1) -#define BPS_DONE_2 BPS_DONE(2) -#define BPS_DONE_3 BPS_DONE(3) -#define BPS_DONE_4 BPS_DONE(4) -#define BPS_DONE_5 BPS_DONE(5) -#define BPS_DONE_6 BPS_DONE(6) -#define BPS_DONE_7 BPS_DONE(7) - -/* - * Buffer n's xfer had an error. - * Clear this bit by issuing bp_clear_buf(n) - */ -#define BPS_ERROR(n) (0x00000100 << (n)) -#define BPS_ERROR_0 BPS_ERROR(0) -#define BPS_ERROR_1 BPS_ERROR(1) -#define BPS_ERROR_2 BPS_ERROR(2) -#define BPS_ERROR_3 BPS_ERROR(3) -#define BPS_ERROR_4 BPS_ERROR(4) -#define BPS_ERROR_5 BPS_ERROR(5) -#define BPS_ERROR_6 BPS_ERROR(6) -#define BPS_ERROR_7 BPS_ERROR(7) - -/* - * Buffer n is idle. A buffer is idle if it's not - * DONE, ERROR, or processing a transaction. If it's - * IDLE, it's safe to start a new transaction. - * - * Clear this bit by starting a xfer with - * bp_send_from_buf or bp_receive_to_buf. - */ -#define BPS_IDLE(n) (0x00010000 << (n)) -#define BPS_IDLE_0 BPS_IDLE(0) -#define BPS_IDLE_1 BPS_IDLE(1) -#define BPS_IDLE_2 BPS_IDLE(2) -#define BPS_IDLE_3 BPS_IDLE(3) -#define BPS_IDLE_4 BPS_IDLE(4) -#define BPS_IDLE_5 BPS_IDLE(5) -#define BPS_IDLE_6 BPS_IDLE(6) -#define BPS_IDLE_7 BPS_IDLE(7) - -/* - * Buffer n has a "slow path" packet in it. - * This bit is orthogonal to the bits above and indicates that - * the FPGA ethernet rx protocol engine has identified this packet - * as one requiring firmware intervention. - */ -#define BPS_SLOWPATH(n) (0x01000000 << (n)) -#define BPS_SLOWPATH_0 BPS_SLOWPATH(0) -#define BPS_SLOWPATH_1 BPS_SLOWPATH(1) -#define BPS_SLOWPATH_2 BPS_SLOWPATH(2) -#define BPS_SLOWPATH_3 BPS_SLOWPATH(3) -#define BPS_SLOWPATH_4 BPS_SLOWPATH(4) -#define BPS_SLOWPATH_5 BPS_SLOWPATH(5) -#define BPS_SLOWPATH_6 BPS_SLOWPATH(6) -#define BPS_SLOWPATH_7 BPS_SLOWPATH(7) - - -#define BPS_DONE_ALL 0x000000ff // mask of all dones -#define BPS_ERROR_ALL 0x0000ff00 // mask of all errors -#define BPS_IDLE_ALL 0x00ff0000 // mask of all idles -#define BPS_SLOWPATH_ALL 0xff000000 // mask of all slowpaths - // The hw_config register #define HWC_SIMULATION 0x80000000 @@ -306,7 +204,7 @@ hwconfig_wishbone_divisor(void) /////////////////////////////////////////////////// // Ethernet Core, Slave 6 -#define ETH_BASE 0x3400 +#define ETH_BASE 0x6400 #include "eth_mac_regs.h" @@ -319,11 +217,7 @@ hwconfig_wishbone_divisor(void) // 1KB of address space (== 256 32-bit write-only regs) -#define MISC_OUTPUT_BASE 0x2000 -#define TX_PROTOCOL_ENGINE_BASE 0x2080 -#define RX_PROTOCOL_ENGINE_BASE 0x20C0 -#define BUFFER_POOL_CTRL_BASE 0x2100 -#define LAST_SETTING_REG 0x23FC // last valid setting register +#define MISC_OUTPUT_BASE 0x5000 #define SR_MISC 0 #define SR_TX_PROT_ENG 32 @@ -340,53 +234,20 @@ hwconfig_wishbone_divisor(void) #define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) +#define SR_ADDR_BLDRDONE _SR_ADDR(5) + // --- buffer pool control regs --- typedef struct { - volatile uint32_t ctrl; + volatile uint32_t misc_ctrl; + volatile uint32_t ip_addr; + volatile uint32_t ctrl_ports; //ctrl (low 16) other (high 16) + volatile uint32_t data_ports; //dsp0 (low 16) dsp1 (high 16) + volatile uint32_t cpu_out_ctrl; + volatile uint32_t cpu_inp_ctrl; } buffer_pool_ctrl_t; -// buffer pool ports - -#define PORT_SERDES 0 // serial/deserializer -#define PORT_DSP 1 // DSP tx or rx pipeline -#define PORT_ETH 2 // ethernet tx or rx -#define PORT_RAM 3 // RAM tx or rx - -// the buffer pool ctrl register fields - -#define BPC_BUFFER(n) (((n) & 0xf) << 28) -#define BPC_BUFFER_MASK BPC_BUFFER(~0) -#define BPC_BUFFER_0 BPC_BUFFER(0) -#define BPC_BUFFER_1 BPC_BUFFER(1) -#define BPC_BUFFER_2 BPC_BUFFER(2) -#define BPC_BUFFER_3 BPC_BUFFER(3) -#define BPC_BUFFER_4 BPC_BUFFER(4) -#define BPC_BUFFER_5 BPC_BUFFER(5) -#define BPC_BUFFER_6 BPC_BUFFER(6) -#define BPC_BUFFER_7 BPC_BUFFER(7) -#define BPC_BUFFER_NIL BPC_BUFFER(0x8) // disable - -#define BPC_PORT(n) (((n) & 0x7) << 25) -#define BPC_PORT_MASK BPC_PORT(~0) -#define BPC_PORT_SERDES BPC_PORT(PORT_SERDES) -#define BPC_PORT_DSP BPC_PORT(PORT_DSP) -#define BPC_PORT_ETH BPC_PORT(PORT_ETH) -#define BPC_PORT_RAM BPC_PORT(PORT_RAM) -#define BPC_PORT_NIL BPC_PORT(0x4) // disable - -#define BPC_CLR (1 << 24) // mutually excl commands -#define BPC_READ (1 << 23) -#define BPC_WRITE (1 << 22) - -#define BPC_STEP(step) (((step) & 0xf) << 18) -#define BPC_STEP_MASK BPC_STEP(~0) -#define BPC_LAST_LINE(line) (((line) & 0x1ff) << 9) -#define BPC_LAST_LINE_MASK BPC_LAST_LINE(~0) -#define BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0) -#define BPC_FIRST_LINE_MASK BPC_FIRST_LINE(~0) - -#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE) +#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) _SR_ADDR(SR_BUFFER_POOL_CTRL)) // --- misc outputs --- @@ -679,7 +540,7 @@ typedef struct { volatile uint32_t seqno; // Write to init seqno. It autoincs on match } tx_proto_engine_regs_t; -#define tx_proto_engine ((tx_proto_engine_regs_t *) TX_PROTOCOL_ENGINE_BASE) +#define tx_proto_engine ((tx_proto_engine_regs_t *) _SR_ADDR(SR_TX_PROT_ENG)) /* * --- ethernet rx protocol engine regs (write only) --- @@ -706,14 +567,14 @@ typedef struct { volatile uint32_t ethertype_pad; // ethertype in high 16-bits } rx_proto_engine_regs_t; -#define rx_proto_engine ((rx_proto_engine_regs_t *) RX_PROTOCOL_ENGINE_BASE) +#define rx_proto_engine ((rx_proto_engine_regs_t *) _SR_ADDR(SR_RX_PROT_ENG)) /////////////////////////////////////////////////// // Simple Programmable Interrupt Controller, Slave 8 -#define PIC_BASE 0x3500 +#define PIC_BASE 0x6500 // Interrupt request lines // Bit numbers (LSB == 0) that correpond to interrupts into PIC @@ -773,7 +634,7 @@ typedef struct { /////////////////////////////////////////////////// // UART, Slave 10 -#define UART_BASE 0x3700 +#define UART_BASE 0x6700 typedef struct { // All elements are 8 bits except for clkdiv (16), but we use uint32 to make @@ -791,7 +652,7 @@ typedef struct { /////////////////////////////////////////////////// // ATR Controller, Slave 11 -#define ATR_BASE 0x3800 +#define ATR_BASE 0x6800 typedef struct { volatile uint32_t v[16]; @@ -810,7 +671,7 @@ typedef struct { /////////////////////////////////////////////////// // ICAP, Slave 13 -#define ICAP_BASE 0x3A00 +#define ICAP_BASE 0x6A00 typedef struct { uint32_t icap; //only the lower 8 bits matter } icap_regs_t; @@ -822,7 +683,7 @@ typedef struct { // Control register definitions are the same as SPI, so use SPI_CTRL_ASS, etc. // Peripheral mask not needed since bus is dedicated (CE held low) -#define SPIF_BASE 0x3B00 +#define SPIF_BASE 0x6B00 typedef struct { volatile uint32_t txrx0; volatile uint32_t txrx1; |