diff options
Diffstat (limited to 'firmware/fx3/b200/b200_gpifconfig.h')
| -rw-r--r-- | firmware/fx3/b200/b200_gpifconfig.h | 178 |
1 files changed, 178 insertions, 0 deletions
diff --git a/firmware/fx3/b200/b200_gpifconfig.h b/firmware/fx3/b200/b200_gpifconfig.h new file mode 100644 index 000000000..58836fac8 --- /dev/null +++ b/firmware/fx3/b200/b200_gpifconfig.h @@ -0,0 +1,178 @@ +//
+// Copyright 2013-2014 Ettus Research LLC
+//
+
+/*
+ * Project Name: b200_v2.cyfx
+ * Time : 01/17/2013 12:50:08
+ * Device Type: FX3
+ * Project Type: GPIF2
+ *
+ *
+ *
+ *
+ * This is a generated file and should not be modified
+ * This file need to be included only once in the firmware
+ * This file is generated by Gpif2 designer tool version - 1.0.715.0
+ *
+ */
+
+#ifndef _INCLUDED_CYFXGPIF2CONFIG_
+#define _INCLUDED_CYFXGPIF2CONFIG_
+#include "cyu3types.h"
+#include "cyu3gpif.h"
+
+/* Summary
+ Number of states in the state machine
+ */
+#define CY_NUMBER_OF_STATES 6
+
+/* Summary
+ Mapping of user defined state names to state indices
+ */
+#define RESET 0
+#define IDLE 1
+#define READ 2
+#define WRITE 3
+#define SHORT_PKT 4
+#define ZLP 5
+
+
+/* Summary
+ Initial value of early outputs from the state machine.
+ */
+#define ALPHA_RESET 0x8
+
+
+/* Summary
+ Transition function values used in the state machine.
+ */
+uint16_t CyFxGpifTransition[] = {
+ 0x0000, 0x8080, 0x2222, 0x5555, 0x7F7F, 0x1F1F, 0x8888
+};
+
+/* Summary
+ Table containing the transition information for various states.
+ This table has to be stored in the WAVEFORM Registers.
+ This array consists of non-replicated waveform descriptors and acts as a
+ waveform table.
+ */
+CyU3PGpifWaveData CyFxGpifWavedata[] = {
+ {{0x1E086001,0x000100C4,0x80000000},{0x00000000,0x00000000,0x00000000}},
+ {{0x4E080302,0x00000200,0x80000000},{0x00000000,0x00000000,0x00000000}},
+ {{0x1E086001,0x000100C4,0x80000000},{0x4E040704,0x20000200,0xC0100000}},
+ {{0x00000000,0x00000000,0x00000000},{0x00000000,0x00000000,0x00000000}},
+ {{0x00000000,0x00000000,0x00000000},{0x3E738705,0x00000200,0xC0100000}},
+ {{0x00000000,0x00000000,0x00000000},{0x5E002703,0x2001020C,0x80000000}},
+ {{0x00000000,0x00000000,0x00000000},{0x4E040704,0x20000200,0xC0100000}}
+};
+
+/* Summary
+ Table that maps state indices to the descriptor table indices.
+ */
+uint8_t CyFxGpifWavedataPosition[] = {
+ 0,1,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 0,4,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 0,5,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 0,6,0,2,0,0
+};
+
+/* Summary
+ GPIF II configuration register values.
+ */
+uint32_t CyFxGpifRegValue[] = {
+ 0x80000380, /* CY_U3P_PIB_GPIF_CONFIG */
+ 0x000010AC, /* CY_U3P_PIB_GPIF_BUS_CONFIG */
+ 0x01070002, /* CY_U3P_PIB_GPIF_BUS_CONFIG2 */
+ 0x00000044, /* CY_U3P_PIB_GPIF_AD_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_STATUS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INTR */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INTR_MASK */
+ 0x00000082, /* CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */
+ 0x00000782, /* CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */
+ 0x00000500, /* CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */
+ 0x0000FFCF, /* CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */
+ 0x000000BF, /* CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000018, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000019, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000006, /* CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */
+ 0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */
+ 0x0000010A, /* CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */
+ 0x0000FFFF, /* CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */
+ 0x0000FFFF, /* CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */
+ 0x0000010A, /* CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COUNT_RESET */
+ 0x0000FFFF, /* CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_MASK */
+ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_VALUE */
+ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_MASK */
+ 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */
+ 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_MASK */
+ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_CTRL */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
+ 0x80010400, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
+ 0x80010401, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
+ 0x80010402, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
+ 0x80010403, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_LAMBDA_STAT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_ALPHA_STAT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_BETA_STAT */
+ 0x00080000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */
+ 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CRC_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CRC_DATA */
+ 0xFFFFFFF1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */
+};
+
+/* Summary
+ This structure holds all the configuration inputs for the GPIF II.
+ */
+const CyU3PGpifConfig_t CyFxGpifConfig = {
+ (uint16_t)(sizeof(CyFxGpifWavedataPosition)/sizeof(uint8_t)),
+ CyFxGpifWavedata,
+ CyFxGpifWavedataPosition,
+ (uint16_t)(sizeof(CyFxGpifTransition)/sizeof(uint16_t)),
+ CyFxGpifTransition,
+ (uint16_t)(sizeof(CyFxGpifRegValue)/sizeof(uint32_t)),
+ CyFxGpifRegValue
+};
+
+#endif /* _INCLUDED_CYFXGPIF2CONFIG_ */
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