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-rw-r--r--firmware/fx2/b100/usb_descriptors.a5148
-rw-r--r--firmware/fx2/b100/usrp_common.c12
-rw-r--r--firmware/fx2/b100/usrp_main.c2
3 files changed, 33 insertions, 29 deletions
diff --git a/firmware/fx2/b100/usb_descriptors.a51 b/firmware/fx2/b100/usb_descriptors.a51
index 6efeb8367..847face16 100644
--- a/firmware/fx2/b100/usb_descriptors.a51
+++ b/firmware/fx2/b100/usb_descriptors.a51
@@ -211,8 +211,8 @@ _high_speed_config_descr::
.db DSCR_ENDPNT
.db 0x04 ; bEndpointAddress (ep 4 OUT)
.db ET_BULK ; bmAttributes
- .db <32 ; wMaxPacketSize (LSB)
- .db >32 ; wMaxPacketSize (MSB)
+ .db <512 ; wMaxPacketSize (LSB)
+ .db >512 ; wMaxPacketSize (MSB)
.db 0 ; bInterval (iso only)
;; interface descriptor 4 (FPGA command IN path, ep8 IN BULK)
@@ -233,8 +233,8 @@ _high_speed_config_descr::
.db DSCR_ENDPNT
.db 0x88 ; bEndpointAddress (ep 8 IN)
.db ET_BULK ; bmAttributes
- .db <32 ; wMaxPacketSize (LSB)
- .db >32 ; wMaxPacketSize (MSB)
+ .db <512 ; wMaxPacketSize (LSB)
+ .db >512 ; wMaxPacketSize (MSB)
.db 0 ; bInterval (iso only)
@@ -341,25 +341,24 @@ str0_end:
.even
str1: .db str1_end - str1
.db DSCR_STRING
- .db 'F, 0 ; 16-bit unicode
- .db 'r, 0
+ .db 'E, 0 ; 16-bit unicode
+ .db 't, 0
+ .db 't, 0
+ .db 'u, 0
+ .db 's, 0
+ .db ' , 0
+ .db 'R, 0
.db 'e, 0
+ .db 's, 0
.db 'e, 0
- .db ' , 0
- .db 'S, 0
- .db 'o, 0
- .db 'f, 0
- .db 't, 0
- .db 'w, 0
.db 'a, 0
.db 'r, 0
- .db 'e, 0
+ .db 'c, 0
+ .db 'h, 0
.db ' , 0
- .db 'F, 0
- .db 'o, 0
- .db 'l, 0
- .db 'k, 0
- .db 's, 0
+ .db 'L, 0
+ .db 'L, 0
+ .db 'C, 0
str1_end:
SI_PRODUCT = 2
@@ -370,13 +369,12 @@ str2: .db str2_end - str2
.db 'S, 0
.db 'R, 0
.db 'P, 0
- .db '1, 0
- .db 'P, 0
- .db ' , 0
- .db 'R, 0
- .db 'e, 0
- .db 'v, 0
- .db ' , 0
+ .db ' , 0
+ .db 'B, 0
+ .db '1, 0
+ .db '0, 0
+ .db '0, 0
+
_usb_desc_hw_rev_ascii_patch_location_0::
.db '?, 0
str2_end:
diff --git a/firmware/fx2/b100/usrp_common.c b/firmware/fx2/b100/usrp_common.c
index a21353688..968b03d48 100644
--- a/firmware/fx2/b100/usrp_common.c
+++ b/firmware/fx2/b100/usrp_common.c
@@ -85,8 +85,8 @@ init_usrp (void)
// set autoin length for EP6/EP8
EP6AUTOINLENH = (512) >> 8; SYNCDELAY; // this is the length for high speed
EP6AUTOINLENL = (512) & 0xff; SYNCDELAY;
- EP8AUTOINLENH = (32) >> 8; SYNCDELAY;
- EP8AUTOINLENL = (32) & 0xff; SYNCDELAY;
+ EP8AUTOINLENH = (512) >> 8; SYNCDELAY;
+ EP8AUTOINLENL = (512) & 0xff; SYNCDELAY;
//set FLAGA, FLAGB, FLAGC, FLAGD to be EP2EF, EP4EF, EP6PF, EP8PF
PINFLAGSAB = (bmEP2EF) | (bmEP4EF << 4);
@@ -99,13 +99,19 @@ init_usrp (void)
EP6FIFOPFL = 0xFD;
SYNCDELAY;
+ EP8FIFOPFH = 0x09;
+ SYNCDELAY;
+ EP8FIFOPFL = 0xFD;
+ SYNCDELAY;
+
// EP2FIFOPFH = 0x08;
// SYNCDELAY;
// EP2FIFOPFL = 0x00;
// SYNCDELAY;
//assert FIFOEMPTY one cycle sooner so we get it in time at the FPGA
- EP2FIFOCFG |= bmBIT5;
+ EP2FIFOCFG |= bmBIT5;
+ EP4FIFOCFG |= bmBIT5;
//set FIFOPINPOLAR to normal (active low) mode
FIFOPINPOLAR = 0x00;
diff --git a/firmware/fx2/b100/usrp_main.c b/firmware/fx2/b100/usrp_main.c
index 74427b7d2..f79d3d111 100644
--- a/firmware/fx2/b100/usrp_main.c
+++ b/firmware/fx2/b100/usrp_main.c
@@ -124,7 +124,7 @@ app_vendor_cmd (void)
case VRQ_FW_COMPAT:
EP0BCH = 0;
- EP0BCL = 3;
+ EP0BCL = 4;
break;
default: