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-rw-r--r--eth/rtl/verilog/miim/eth_clockgen.v141
-rw-r--r--eth/rtl/verilog/miim/eth_outputcontrol.v158
-rw-r--r--eth/rtl/verilog/miim/eth_shiftreg.v159
3 files changed, 458 insertions, 0 deletions
diff --git a/eth/rtl/verilog/miim/eth_clockgen.v b/eth/rtl/verilog/miim/eth_clockgen.v
new file mode 100644
index 000000000..9da732f7f
--- /dev/null
+++ b/eth/rtl/verilog/miim/eth_clockgen.v
@@ -0,0 +1,141 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_clockgen.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects/ethmac/ ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_clockgen.v,v $
+// Revision 1.2 2005/12/13 12:54:49 maverickist
+// first simulation passed
+//
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
+// no message
+//
+// Revision 1.2 2005/04/27 15:58:45 Administrator
+// no message
+//
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
+// no message
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:55 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
+
+//parameter Tp=1;
+
+input Clk; // Input clock (Host clock)
+input Reset; // Reset signal
+input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
+
+output Mdc; // Output clock
+output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
+output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
+
+reg Mdc;
+reg [7:0] Counter;
+
+wire CountEq0;
+wire [7:0] CounterPreset;
+wire [7:0] TempDivider;
+
+
+assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
+assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period
+
+
+// Counter counts half period
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ Counter[7:0] <= 8'h1;
+ else
+ begin
+ if(CountEq0)
+ begin
+ Counter[7:0] <= CounterPreset[7:0];
+ end
+ else
+ Counter[7:0] <= Counter - 8'h1;
+ end
+end
+
+
+// Mdc is asserted every other half period
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ Mdc <= 1'b0;
+ else
+ begin
+ if(CountEq0)
+ Mdc <= ~Mdc;
+ end
+end
+
+
+assign CountEq0 = Counter == 8'h0;
+assign MdcEn = CountEq0 & ~Mdc;
+assign MdcEn_n = CountEq0 & Mdc;
+
+endmodule
+
+
diff --git a/eth/rtl/verilog/miim/eth_outputcontrol.v b/eth/rtl/verilog/miim/eth_outputcontrol.v
new file mode 100644
index 000000000..3df6c560a
--- /dev/null
+++ b/eth/rtl/verilog/miim/eth_outputcontrol.v
@@ -0,0 +1,158 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_outputcontrol.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects/ethmac/ ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_outputcontrol.v,v $
+// Revision 1.2 2005/12/13 12:54:49 maverickist
+// first simulation passed
+//
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
+// no message
+//
+// Revision 1.2 2005/04/27 15:58:46 Administrator
+// no message
+//
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
+// no message
+//
+// Revision 1.4 2002/07/09 20:11:59 mohor
+// Comment removed.
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:56 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
+
+input Clk; // Host Clock
+input Reset; // General Reset
+input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
+input NoPre; // No Preamble (no 32-bit preamble)
+input InProgress; // Operation in progress
+input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
+input [6:0] BitCounter; // Bit Counter
+input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
+
+output Mdo; // MII Management Data Output
+output MdoEn; // MII Management Data Output Enable
+
+wire SerialEn;
+
+reg MdoEn_2d;
+reg MdoEn_d;
+reg MdoEn;
+
+reg Mdo_2d;
+reg Mdo_d;
+reg Mdo; // MII Management Data Output
+
+
+
+// Generation of the Serial Enable signal (enables the serialization of the data)
+assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
+ | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
+
+
+// Generation of the MdoEn signal
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ MdoEn_2d <= 1'b0;
+ MdoEn_d <= 1'b0;
+ MdoEn <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn_n)
+ begin
+ MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
+ MdoEn_d <= MdoEn_2d;
+ MdoEn <= MdoEn_d;
+ end
+ end
+end
+
+
+// Generation of the Mdo signal.
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ Mdo_2d <= 1'b0;
+ Mdo_d <= 1'b0;
+ Mdo <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn_n)
+ begin
+ Mdo_2d <= ~SerialEn & BitCounter<32;
+ Mdo_d <= ShiftedBit | Mdo_2d;
+ Mdo <= Mdo_d;
+ end
+ end
+end
+
+
+
+endmodule
diff --git a/eth/rtl/verilog/miim/eth_shiftreg.v b/eth/rtl/verilog/miim/eth_shiftreg.v
new file mode 100644
index 000000000..0b97bb7bc
--- /dev/null
+++ b/eth/rtl/verilog/miim/eth_shiftreg.v
@@ -0,0 +1,159 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_shiftreg.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects/ethmac/ ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_shiftreg.v,v $
+// Revision 1.2 2005/12/13 12:54:49 maverickist
+// first simulation passed
+//
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
+// no message
+//
+// Revision 1.2 2005/04/27 15:58:47 Administrator
+// no message
+//
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
+// no message
+//
+// Revision 1.5 2002/08/14 18:16:59 mohor
+// LinkFail signal was not latching appropriate bit.
+//
+// Revision 1.4 2002/03/02 21:06:01 mohor
+// LinkFail signal was not latching appropriate bit.
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:56 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
+ LatchByte, ShiftedBit, Prsd, LinkFail);
+
+
+input Clk; // Input clock (Host clock)
+input Reset; // Reset signal
+input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
+input Mdi; // MII input data
+input [4:0] Fiad; // PHY address
+input [4:0] Rgad; // Register address (within the selected PHY)
+input [15:0]CtrlData; // Control data (data to be written to the PHY)
+input WriteOp; // The current operation is a PHY register write operation
+input [3:0] ByteSelect; // Byte select
+input [1:0] LatchByte; // Byte select for latching (read operation)
+
+output ShiftedBit; // Bit shifted out of the shift register
+output[15:0]Prsd; // Read Status Data (data read from the PHY)
+output LinkFail; // Link Integrity Signal
+
+reg [7:0] ShiftReg; // Shift register for shifting the data in and out
+reg [15:0]Prsd;
+reg LinkFail;
+
+
+
+
+// ShiftReg[7:0] :: Shift Register Data
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ ShiftReg[7:0] <= 8'h0;
+ Prsd[15:0] <= 16'h0;
+ LinkFail <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn_n)
+ begin
+ if(|ByteSelect)
+ begin
+ case (ByteSelect[3:0])
+ 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
+ 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
+ 4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
+ 4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
+ default : ShiftReg[7:0] <= 8'h0;
+ endcase
+ end
+ else
+ begin
+ ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
+ if(LatchByte[0])
+ begin
+ Prsd[7:0] <= {ShiftReg[6:0], Mdi};
+ if(Rgad == 5'h01)
+ LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
+ end
+ else
+ begin
+ if(LatchByte[1])
+ Prsd[15:8] <= {ShiftReg[6:0], Mdi};
+ end
+ end
+ end
+ end
+end
+
+
+assign ShiftedBit = ShiftReg[7];
+
+
+endmodule
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