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-rw-r--r--control_lib/buffer_int.v251
-rw-r--r--control_lib/buffer_int_tb.v447
-rw-r--r--control_lib/buffer_pool.v323
-rw-r--r--control_lib/buffer_pool_tb.v50
-rw-r--r--control_lib/cascadefifo.v50
-rw-r--r--control_lib/cascadefifo2.v56
-rw-r--r--control_lib/fifo_2clock.v66
-rw-r--r--control_lib/fifo_2clock_casc.v31
-rw-r--r--control_lib/fifo_reader.v28
-rw-r--r--control_lib/fifo_tb.v8
-rw-r--r--control_lib/fifo_writer.v31
-rw-r--r--control_lib/giantfifo.v209
-rw-r--r--control_lib/giantfifo_tb.v173
-rw-r--r--control_lib/newfifo/.gitignore1
-rw-r--r--control_lib/newfifo/fifo18_to_ll8.v58
-rw-r--r--control_lib/newfifo/fifo36_to_ll8.v2
-rw-r--r--control_lib/newfifo/fifo_2clock.v61
-rw-r--r--control_lib/newfifo/fifo_2clock_casc.v31
-rw-r--r--control_lib/newfifo/fifo_2clock_cascade.v35
-rw-r--r--control_lib/newfifo/fifo_new_tb.v158
-rw-r--r--control_lib/newfifo/fifo_tb.v257
-rw-r--r--control_lib/newfifo/ll8_shortfifo.v13
-rw-r--r--control_lib/wb_1master.v318
23 files changed, 414 insertions, 2243 deletions
diff --git a/control_lib/buffer_int.v b/control_lib/buffer_int.v
deleted file mode 100644
index c33f2779d..000000000
--- a/control_lib/buffer_int.v
+++ /dev/null
@@ -1,251 +0,0 @@
-
-// FIFO Interface to the 2K buffer RAMs
-// Read port is read-acknowledge
-// FIXME do we want to be able to interleave reads and writes?
-
-module buffer_int
- #(parameter BUFF_NUM = 0)
- (// Control Interface
- input clk,
- input rst,
- input [31:0] ctrl_word,
- input go,
- output done,
- output error,
- output idle,
-
- // Buffer Interface
- output en_o,
- output we_o,
- output reg [8:0] addr_o,
- output [31:0] dat_to_buf,
- input [31:0] dat_from_buf,
-
- // Write FIFO Interface
- input [31:0] wr_dat_i,
- input wr_write_i,
- input wr_done_i,
- input wr_error_i,
- output reg wr_ready_o,
- output reg wr_full_o,
-
- // Read FIFO Interface
- output [31:0] rd_dat_o,
- input rd_read_i,
- input rd_done_i,
- input rd_error_i,
- output reg rd_sop_o,
- output reg rd_eop_o
- );
-
- reg [31:0] ctrl_reg;
- reg go_reg;
-
- always @(posedge clk)
- go_reg <= go;
-
- always @(posedge clk)
- if(rst)
- ctrl_reg <= 0;
- else
- if(go & (ctrl_word[31:28] == BUFF_NUM))
- ctrl_reg <= ctrl_word;
-
- wire [8:0] firstline = ctrl_reg[8:0];
- wire [8:0] lastline = ctrl_reg[17:9];
- wire [3:0] step = ctrl_reg[21:18];
- wire read = ctrl_reg[22];
- wire write = ctrl_reg[23];
- wire clear = ctrl_reg[24];
- //wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block
- //wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ?
-
- assign dat_to_buf = wr_dat_i;
- assign rd_dat_o = dat_from_buf;
-
- localparam IDLE = 3'd0;
- localparam PRE_READ = 3'd1;
- localparam READING = 3'd2;
- localparam WRITING = 3'd3;
- localparam ERROR = 3'd4;
- localparam DONE = 3'd5;
-
- reg [2:0] state;
-
- always @(posedge clk)
- if(rst)
- begin
- state <= IDLE;
- rd_sop_o <= 0;
- rd_eop_o <= 0;
- wr_ready_o <= 0;
- wr_full_o <= 0;
- end
- else
- if(clear)
- begin
- state <= IDLE;
- rd_sop_o <= 0;
- rd_eop_o <= 0;
- wr_ready_o <= 0;
- wr_full_o <= 0;
- end
- else
- case(state)
- IDLE :
- if(go_reg & read)
- begin
- addr_o <= firstline;
- state <= PRE_READ;
- end
- else if(go_reg & write)
- begin
- addr_o <= firstline;
- state <= WRITING;
- wr_ready_o <= 1;
- end
-
- PRE_READ :
- begin
- state <= READING;
- addr_o <= addr_o + 1;
- rd_sop_o <= 1;
- end
-
- READING :
- if(rd_error_i)
- state <= ERROR;
- else if(rd_done_i)
- state <= DONE;
- else if(rd_read_i)
- begin
- rd_sop_o <= 0;
- addr_o <= addr_o + 1;
- if(addr_o == lastline)
- rd_eop_o <= 1;
- else
- rd_eop_o <= 0;
- if(rd_eop_o)
- state <= DONE;
- end
-
- WRITING :
- begin
- if(wr_write_i)
- addr_o <= addr_o + 1; // This was the timing problem, so now it doesn't depend on wr_error_i
- if(wr_error_i)
- begin
- state <= ERROR;
- wr_ready_o <= 0;
- end
- else
- begin
- if(wr_write_i)
- begin
- wr_ready_o <= 0;
- if(addr_o == (lastline-1))
- wr_full_o <= 1;
- if(addr_o == lastline)
- state <= DONE;
- end
- if(wr_done_i)
- begin
- state <= DONE;
- wr_ready_o <= 0;
- end
- end // else: !if(wr_error_i)
- end // case: WRITING
-
- DONE :
- begin
- rd_eop_o <= 0;
- rd_sop_o <= 0;
- wr_ready_o <= 0;
- wr_full_o <= 0;
- end
-
- endcase // case(state)
-
- // FIXME ignores step for now
-
- assign we_o = (state == WRITING) && wr_write_i; // FIXME potential critical path
- // IF this is a timing problem, we could always write when in this state
- assign en_o = ~((state==READING)& ~rd_read_i); // FIXME potential critical path
-
- assign done = (state == DONE);
- assign error = (state == ERROR);
- assign idle = (state == IDLE);
-endmodule // buffer_int
-
-
-
-// These are 2 other ways for doing the WRITING state, both work. First one is faster, but confusing
-/*
- begin
- // Gen 4 values -- state, wr_ready_o, addr_o, wr_full_o
- if(~wr_error_i & wr_write_i & (addr_o == (lastline-1)))
- wr_full_o <= 1;
- if(wr_error_i | wr_write_i | wr_done_i)
- wr_ready_o <= 0;
- if(wr_error_i)
- state <= ERROR;
- else if(wr_done_i | (wr_write_i & (addr_o == lastline)))
- state <= DONE;
- // This one was the timing problem... now we increment addr_o even if there is an error
- if(wr_write_i)
- addr_o <= addr_o + 1;
- end // case: WRITING
-*/
-
-/* begin
- if(wr_error_i)
- begin
- state <= ERROR;
- wr_ready_o <= 0;
- end
- else
- begin
- if(wr_write_i)
- begin
- wr_ready_o <= 0;
- addr_o <= addr_o + 1;
- if(addr_o == (lastline-1))
- wr_full_o <= 1;
- if(addr_o == lastline)
- state <= DONE;
- end
- if(wr_done_i)
- begin
- state <= DONE;
- wr_ready_o <= 0;
- end
- end // else: !if(wr_error_i)
- end // case: WRITING
-*/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-// Unused old code
- //assign rd_empty_o = (state != READING); // && (state != PRE_READ);
- //assign rd_empty_o = rd_empty_reg; // timing fix?
- //assign rd_ready_o = (state == READING);
- //assign rd_ready_o = ~rd_empty_reg; // timing fix?
-
- //wire rd_en = (state == PRE_READ) || ((state == READING) && rd_read_i);
- //wire wr_en = (state == WRITING) && wr_write_i; // IF this is a timing problem, we could always enable when in this state
- //assign en_o = rd_en | wr_en;
-
- // assign wr_full_o = (state != WRITING);
- // assign wr_ready_o = (state == WRITING);
-
diff --git a/control_lib/buffer_int_tb.v b/control_lib/buffer_int_tb.v
deleted file mode 100644
index 4fb5c6710..000000000
--- a/control_lib/buffer_int_tb.v
+++ /dev/null
@@ -1,447 +0,0 @@
-
-module buffer_int_tb ();
-
- reg clk = 0;
- reg rst = 1;
-
- initial #100 rst = 0;
- always #5 clk = ~clk;
-
- wire en, we;
- wire [8:0] addr;
- wire [31:0] fifo2buf, buf2fifo;
-
- wire [31:0] rd_dat_o;
- wire rd_sop_o, rd_eop_o;
- reg rd_done_i = 0, rd_error_i = 0, rd_read_i = 0;
-
- reg [31:0] wr_dat_i = 0;
- reg wr_write_i=0, wr_done_i = 0, wr_error_i = 0;
- wire wr_ready_o, wr_full_o;
-
- reg clear = 0, write = 0, read = 0;
- reg [8:0] firstline = 0, lastline = 0;
- wire [3:0] step = 1;
- wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline};
- reg go = 0;
- wire done, error;
-
- buffer_int buffer_int
- (.clk(clk),.rst(rst),
- .ctrl_word(ctrl_word),.go(go),
- .done(done),.error(error),
-
- // Buffer Interface
- .en_o(en),.we_o(we),.addr_o(addr),
- .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
-
- // Write FIFO Interface
- .wr_dat_i(wr_dat_i), .wr_write_i(wr_write_i), .wr_done_i(wr_done_i), .wr_error_i(wr_error_i),
- .wr_ready_o(wr_ready_o), .wr_full_o(wr_full_o),
-
- // Read FIFO Interface
- .rd_dat_o(rd_dat_o), .rd_read_i(rd_read_i), .rd_done_i(rd_done_i), .rd_error_i(rd_error_i),
- .rd_sop_o(rd_sop_o), .rd_eop_o(rd_eop_o)
- );
-
- reg ram_en = 0, ram_we = 0;
- reg [8:0] ram_addr = 0;
- reg [31:0] ram_data = 0;
-
- ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port
- (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(),
- .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) );
-
- initial
- begin
- @(negedge rst);
- @(posedge clk);
- FillRAM;
-
- ResetBuffer;
- SetBufferRead(5,10);
- $display("Testing full read, no wait states.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(6,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(5,10);
- $display("Testing full read, 2 wait states.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(6,2);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(5,10);
- $display("Testing full read, done ON the last.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(5,2);
- rd_done_i <= 1;
- ReadALine;
- rd_done_i <= 0;
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(5,10);
- $display("Testing partial read, 0 wait states, then nothing after last.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(3,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(5,10);
- $display("Testing partial read, 0 wait states, then done after last.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(3,0);
- rd_done_i <= 1;
- @(posedge clk);
- rd_done_i <= 0;
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(5,10);
- $display("Testing partial read, 0 wait states, then done at same time as last.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(2,0);
- rd_done_i <= 1;
- ReadALine;
- rd_done_i <= 0;
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(5,10);
- $display("Testing partial read, 3 wait states, then error at same time as last.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(2,3);
- rd_error_i <= 1;
- ReadALine;
- rd_error_i <= 0;
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(5,10);
- $display("Testing Reading too much, 3 wait states.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(9,3);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(500,511);
- $display("Testing full read, to the end of the buffer.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(12,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(0,511);
- $display("Testing full read, start to end of the buffer.");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(512,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(505,3);
- $display("Testing full read, wraparound");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(11,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(10,15);
- $display("Testing Full Write, no wait states");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(6,0,72);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(18,23);
- $display("Testing Full Write, 1 wait states");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(6,0,101);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(27,40);
- $display("Testing Partial Write, 0 wait states");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(6,0,201);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(35,200);
- $display("Testing Partial Write, 0 wait states, then done");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(6,0,301);
- wr_done_i <= 1;
- @(posedge clk);
- wr_done_i <= 0;
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(45,200);
- $display("Testing Partial Write, 0 wait states, then done and write simultaneously");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(6,0,301);
- wr_done_i <= 1;
- WriteALine(400);
- wr_done_i <= 0;
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(55,200);
- $display("Testing Partial Write, 0 wait states, then error");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(6,0,501);
- wr_error_i <= 1;
- @(posedge clk);
- wr_error_i <= 0;
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(0,82);
- $display("Testing read after all the writes");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(83,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(508,4);
- $display("Testing wraparound write");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(9,0,601);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(506,10);
- $display("Reading wraparound write");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(17,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(0,511);
- $display("Testing Whole Buffer write");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(512,0,1000);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(0,511);
- $display("Reading Whole Buffer write");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(512,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(5,10);
- $display("Testing Write Too Many");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(12,0,2000);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(0,15);
- $display("Reading back Write Too Many");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(16,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferWrite(15,20);
- $display("Testing Write One Less Than Full");
- while(!wr_ready_o)
- @(posedge clk);
- WriteLines(5,0,2000);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- SetBufferRead(13,22);
- $display("Reading back Write One Less Than Full");
- while(!rd_sop_o)
- @(posedge clk);
- ReadLines(10,0);
- repeat (10)
- @(posedge clk);
-
- ResetBuffer;
- repeat(100)
- @(posedge clk);
- $finish;
- end
-
- always @(posedge clk)
- if(rd_read_i == 1'd1)
- $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_dat_o, rd_sop_o, rd_eop_o);
-
- always @(posedge clk)
- if(wr_write_i == 1'd1)
- $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_dat_i, wr_ready_o, wr_full_o);
-
- initial begin
- $dumpfile("buffer_int_tb.vcd");
- $dumpvars(0,buffer_int_tb);
- end
-
- task FillRAM;
- begin
- ram_addr <= 0;
- ram_data <= 0;
- @(posedge clk);
- ram_en <= 1;
- ram_we <= 1;
- @(posedge clk);
- repeat (511)
- begin
- ram_addr <= ram_addr + 1;
- ram_data <= ram_data + 1;
- ram_en <= 1;
- ram_we <= 1;
- @(posedge clk);
- end
- ram_en <= 0;
- ram_we <= 0;
- @(posedge clk);
- $display("Filled the RAM");
- end
- endtask // FillRAM
-
- task ResetBuffer;
- begin
- clear <= 1; read <= 0; write <= 0;
- go <= 1;
- @(posedge clk);
- go <= 0;
- @(posedge clk);
- $display("Buffer Reset");
- end
- endtask // ClearBuffer
-
- task SetBufferWrite;
- input [8:0] start;
- input [8:0] stop;
- begin
- clear <= 0; read <= 0; write <= 1;
- firstline <= start;
- lastline <= stop;
- go <= 1;
- @(posedge clk);
- go <= 0;
- @(posedge clk);
- $display("Buffer Set for Write");
- end
- endtask // SetBufferWrite
-
- task SetBufferRead;
- input [8:0] start;
- input [8:0] stop;
- begin
- clear <= 0; read <= 1; write <= 0;
- firstline <= start;
- lastline <= stop;
- go <= 1;
- @(posedge clk);
- go <= 0;
- @(posedge clk);
- $display("Buffer Set for Read");
- end
- endtask // SetBufferRead
-
- task ReadALine;
- begin
- #1 rd_read_i <= 1;
- @(posedge clk);
- rd_read_i <= 0;
- end
- endtask // ReadALine
-
- task ReadLines;
- input [9:0] lines;
- input [7:0] wait_states;
- begin
- $display("Read Lines: Number %d, Wait States %d",lines,wait_states);
- repeat (lines)
- begin
- ReadALine;
- repeat (wait_states)
- @(posedge clk);
- end
- end
- endtask // ReadLines
-
- task WriteALine;
- input [31:0] value;
- begin
- #1 wr_write_i <= 1;
- wr_dat_i <= value;
- @(posedge clk);
- wr_write_i <= 0;
- end
- endtask // WriteALine
-
- task WriteLines;
- input [9:0] lines;
- input [7:0] wait_states;
- input [31:0] value;
- begin
- $display("Write Lines: Number %d, Wait States %d",lines,wait_states);
- repeat(lines)
- begin
- value <= value + 1;
- WriteALine(value);
- repeat(wait_states)
- @(posedge clk);
- end
- end
- endtask // WriteLines
-
-endmodule // buffer_int_tb
diff --git a/control_lib/buffer_pool.v b/control_lib/buffer_pool.v
deleted file mode 100644
index 969296230..000000000
--- a/control_lib/buffer_pool.v
+++ /dev/null
@@ -1,323 +0,0 @@
-
-// Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer
-// is a dual-ported RAM. Port A on each of them is indirectly connected
-// to the wishbone bus by a bridge. Port B may be connected any one of the
-// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected. The wishbone bus
-// provides access to all 8 buffers, and also controls the connections
-// between the ports and the buffers, allocating them as needed.
-
-// wb_adr is 16 bits --
-// bits 13:11 select which buffer
-// bits 10:2 select line in buffer
-// bits 1:0 are unused (32-bit access only)
-
-module buffer_pool
- (input wb_clk_i,
- input wb_rst_i,
- input wb_we_i,
- input wb_stb_i,
- input [15:0] wb_adr_i,
- input [31:0] wb_dat_i,
- output [31:0] wb_dat_o,
- output reg wb_ack_o,
- output wb_err_o,
- output wb_rty_o,
-
- input stream_clk,
- input stream_rst,
-
- input set_stb, input [7:0] set_addr, input [31:0] set_data,
- output [31:0] status,
- output sys_int_o,
-
- output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3,
- output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7,
-
- // Write Interfaces
- input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, input wr0_error_i, output wr0_ready_o, output wr0_full_o,
- input [31:0] wr1_dat_i, input wr1_write_i, input wr1_done_i, input wr1_error_i, output wr1_ready_o, output wr1_full_o,
- input [31:0] wr2_dat_i, input wr2_write_i, input wr2_done_i, input wr2_error_i, output wr2_ready_o, output wr2_full_o,
- input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, input wr3_error_i, output wr3_ready_o, output wr3_full_o,
-
- // Read Interfaces
- output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, input rd0_error_i, output rd0_sop_o, output rd0_eop_o,
- output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, input rd1_error_i, output rd1_sop_o, output rd1_eop_o,
- output [31:0] rd2_dat_o, input rd2_read_i, input rd2_done_i, input rd2_error_i, output rd2_sop_o, output rd2_eop_o,
- output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, input rd3_error_i, output rd3_sop_o, output rd3_eop_o
- );
-
- wire [7:0] sel_a;
-
- wire [2:0] which_buf = wb_adr_i[13:11]; // address 15:14 selects the buffer pool
- wire [8:0] buf_addra = wb_adr_i[10:2]; // ignore address 1:0, 32-bit access only
-
- decoder_3_8 dec(.sel(which_buf),.res(sel_a));
-
- genvar i;
-
- wire go;
-
- reg [2:0] port[0:7];
- reg [3:0] read_src[0:3];
- reg [3:0] write_src[0:3];
-
- wire [7:0] done;
- wire [7:0] error;
- wire [7:0] idle;
-
- wire [31:0] buf_doa[0:7];
-
- wire [7:0] buf_enb;
- wire [7:0] buf_web;
- wire [8:0] buf_addrb[0:7];
- wire [31:0] buf_dib[0:7];
- wire [31:0] buf_dob[0:7];
-
- wire [31:0] wr_dat_i[0:7];
- wire [7:0] wr_write_i;
- wire [7:0] wr_done_i;
- wire [7:0] wr_error_i;
- wire [7:0] wr_ready_o;
- wire [7:0] wr_full_o;
-
- wire [31:0] rd_dat_o[0:7];
- wire [7:0] rd_read_i;
- wire [7:0] rd_done_i;
- wire [7:0] rd_error_i;
- wire [7:0] rd_sop_o;
- wire [7:0] rd_eop_o;
-
- assign status = {8'd0,idle[7:0],error[7:0],done[7:0]};
-
- assign s0 = {23'd0,buf_addrb[0]};
- assign s1 = {23'd0,buf_addrb[1]};
- assign s2 = {23'd0,buf_addrb[2]};
- assign s3 = {23'd0,buf_addrb[3]};
- assign s4 = {23'd0,buf_addrb[4]};
- assign s5 = {23'd0,buf_addrb[5]};
- assign s6 = {23'd0,buf_addrb[6]};
- assign s7 = {23'd0,buf_addrb[7]};
-
- wire [31:0] fifo_ctrl;
- setting_reg #(.my_addr(64))
- sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
- .out(fifo_ctrl),.changed(go));
-
- integer k;
- always @(posedge stream_clk)
- if(stream_rst)
- for(k=0;k<8;k=k+1)
- port[k] <= 4; // disabled
- else
- for(k=0;k<8;k=k+1)
- if(go & (fifo_ctrl[31:28]==k))
- port[k] <= fifo_ctrl[27:25];
-
- always @(posedge stream_clk)
- if(stream_rst)
- for(k=0;k<4;k=k+1)
- read_src[k] <= 8; // disabled
- else
- for(k=0;k<4;k=k+1)
- if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k))
- read_src[k] <= fifo_ctrl[31:28];
-
- always @(posedge stream_clk)
- if(stream_rst)
- for(k=0;k<4;k=k+1)
- write_src[k] <= 8; // disabled
- else
- for(k=0;k<4;k=k+1)
- if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k))
- write_src[k] <= fifo_ctrl[31:28];
-
- generate
- for(i=0;i<8;i=i+1)
- begin : gen_buffer
- RAMB16_S36_S36 dpram
- (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
- .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i),
- .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0),
- .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) );
-
- /* ram_2port #(.DWIDTH(32),.AWIDTH(9)) buffer
- (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
- .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
- .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),
- .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); */
-
- buffer_int #(.BUFF_NUM(i)) fifo_int
- (.clk(stream_clk),.rst(stream_rst),
- .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)),
- .done(done[i]),.error(error[i]),.idle(idle[i]),
- .en_o(buf_enb[i]),
- .we_o(buf_web[i]),
- .addr_o(buf_addrb[i]),
- .dat_to_buf(buf_dib[i]),
- .dat_from_buf(buf_dob[i]),
- .wr_dat_i(wr_dat_i[i]),
- .wr_write_i(wr_write_i[i]),
- .wr_done_i(wr_done_i[i]),
- .wr_error_i(wr_error_i[i]),
- .wr_ready_o(wr_ready_o[i]),
- .wr_full_o(wr_full_o[i]),
- .rd_dat_o(rd_dat_o[i]),
- .rd_read_i(rd_read_i[i]),
- .rd_done_i(rd_done_i[i]),
- .rd_error_i(rd_error_i[i]),
- .rd_sop_o(rd_sop_o[i]),
- .rd_eop_o(rd_eop_o[i])
- );
-
- // FIXME -- if it is a problem, maybe we don't need enables on these muxes
- mux4 #(.WIDTH(32))
- mux4_dat_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_dat_i),.i1(wr1_dat_i),
- .i2(wr2_dat_i),.i3(wr3_dat_i),.o(wr_dat_i[i]));
- mux4 #(.WIDTH(1))
- mux4_write_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_write_i),.i1(wr1_write_i),
- .i2(wr2_write_i),.i3(wr3_write_i),.o(wr_write_i[i]));
- mux4 #(.WIDTH(1))
- mux4_wrdone_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_done_i),.i1(wr1_done_i),
- .i2(wr2_done_i),.i3(wr3_done_i),.o(wr_done_i[i]));
- mux4 #(.WIDTH(1))
- mux4_wrerror_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_error_i),.i1(wr1_error_i),
- .i2(wr2_error_i),.i3(wr3_error_i),.o(wr_error_i[i]));
- mux4 #(.WIDTH(1))
- mux4_read_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_read_i),.i1(rd1_read_i),
- .i2(rd2_read_i),.i3(rd3_read_i),.o(rd_read_i[i]));
- mux4 #(.WIDTH(1))
- mux4_rddone_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_done_i),.i1(rd1_done_i),
- .i2(rd2_done_i),.i3(rd3_done_i),.o(rd_done_i[i]));
- mux4 #(.WIDTH(1))
- mux4_rderror_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_error_i),.i1(rd1_error_i),
- .i2(rd2_error_i),.i3(rd3_error_i),.o(rd_error_i[i]));
- end // block: gen_buffer
- endgenerate
-
- //----------------------------------------------------------------------
- // Wishbone Outputs
-
- // Use the following lines if ram output and mux can be made fast enough
-
- assign wb_err_o = 1'b0; // Unused for now
- assign wb_rty_o = 1'b0; // Unused for now
-
- always @(posedge wb_clk_i)
- wb_ack_o <= wb_stb_i & ~wb_ack_o;
- assign wb_dat_o = buf_doa[which_buf];
-
- // Use this if we can't make the RAM+MUX fast enough
- // reg [31:0] wb_dat_o_reg;
- // reg stb_d1;
-
- // always @(posedge wb_clk_i)
- // begin
- // wb_dat_o_reg <= buf_doa[which_buf];
- // stb_d1 <= wb_stb_i;
- // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i);
- // end
- //assign wb_dat_o = wb_dat_o_reg;
-
- mux8 #(.WIDTH(1))
- mux8_wr_ready0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
- .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
- .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr0_ready_o));
-
- mux8 #(.WIDTH(1))
- mux8_wr_full0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
- .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
- .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr0_full_o));
-
- mux8 #(.WIDTH(1))
- mux8_wr_ready1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
- .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
- .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr1_ready_o));
-
- mux8 #(.WIDTH(1))
- mux8_wr_full1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
- .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
- .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr1_full_o));
-
- mux8 #(.WIDTH(1))
- mux8_wr_ready2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
- .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
- .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr2_ready_o));
-
- mux8 #(.WIDTH(1))
- mux8_wr_full2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
- .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
- .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr2_full_o));
-
- mux8 #(.WIDTH(1))
- mux8_wr_ready3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
- .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
- .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr3_ready_o));
-
- mux8 #(.WIDTH(1))
- mux8_wr_full3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
- .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
- .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr3_full_o));
-
- mux8 #(.WIDTH(1))
- mux8_rd_sop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
- .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
- .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd0_sop_o));
-
- mux8 #(.WIDTH(1))
- mux8_rd_eop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
- .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
- .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd0_eop_o));
-
- mux8 #(.WIDTH(32))
- mux8_rd_dat_0 (.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
- .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
- .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd0_dat_o));
-
- mux8 #(.WIDTH(1))
- mux8_rd_sop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
- .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
- .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd1_sop_o));
-
- mux8 #(.WIDTH(1))
- mux8_rd_eop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
- .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
- .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd1_eop_o));
-
- mux8 #(.WIDTH(32))
- mux8_rd_dat_1 (.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
- .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
- .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd1_dat_o));
-
- mux8 #(.WIDTH(1))
- mux8_rd_sop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
- .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
- .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd2_sop_o));
-
- mux8 #(.WIDTH(1))
- mux8_rd_eop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
- .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
- .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd2_eop_o));
-
- mux8 #(.WIDTH(32))
- mux8_rd_dat_2 (.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
- .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
- .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd2_dat_o));
-
- mux8 #(.WIDTH(1))
- mux8_rd_sop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]),
- .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]),
- .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd3_sop_o));
-
- mux8 #(.WIDTH(1))
- mux8_rd_eop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]),
- .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]),
- .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd3_eop_o));
-
- mux8 #(.WIDTH(32))
- mux8_rd_dat_3 (.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
- .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
- .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd3_dat_o));
-
- assign sys_int_o = (|error) | (|done);
-
-endmodule // buffer_pool
diff --git a/control_lib/buffer_pool_tb.v b/control_lib/buffer_pool_tb.v
deleted file mode 100644
index 16741438e..000000000
--- a/control_lib/buffer_pool_tb.v
+++ /dev/null
@@ -1,50 +0,0 @@
-
-module buffer_pool_tb();
-
- wire wb_clk_i;
- wire wb_rst_i;
- wire wb_we_i;
- wire wb_stb_i;
- wire [15:0] wb_adr_i;
- wire [31:0] wb_dat_i;
- wire [31:0] wb_dat_o;
- wire wb_ack_o;
- wire wb_err_o;
- wire wb_rty_o;
-
- wire stream_clk, stream_rst;
-
- wire set_stb;
- wire [7:0] set_addr;
- wire [31:0] set_data;
-
- wire [31:0] wr0_dat_i;
- buffer_pool dut
- (.wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
- .wb_we_i(wb_we_i),
- .wb_stb_i(wb_stb_i),
- .wb_adr_i(wb_adr_i),
- .wb_dat_i(wb_dat_i),
- .wb_dat_o(wb_dat_o),
- .wb_ack_o(wb_ack_o),
- .wb_err_o(wb_err_o),
- .wb_rty_o(wb_rty_o),
-
- .stream_clk(stream_clk),
- .stream_rst(stream_rst),
-
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-
- .wr0_dat_i(wr0_dat_i), .wr0_write_i(), .wr0_done_i(), .wr0_error_i(), .wr0_ready_o(), .wr0_full_o(),
- .wr1_dat_i(), .wr1_write_i(), .wr1_done_i(), .wr1_error_i(), .wr1_ready_o(), .wr1_full_o(),
- .wr2_dat_i(), .wr2_write_i(), .wr2_done_i(), .wr2_error_i(), .wr2_ready_o(), .wr2_full_o(),
- .wr3_dat_i(), .wr3_write_i(), .wr3_done_i(), .wr3_error_i(), .wr3_ready_o(), .wr3_full_o(),
-
- .rd0_dat_o(), .rd0_read_i(), .rd0_done_i(), .rd0_error_i(), .rd0_ready_o(), .rd0_empty_o(),
- .rd1_dat_o(), .rd1_read_i(), .rd1_done_i(), .rd1_error_i(), .rd1_ready_o(), .rd1_empty_o(),
- .rd2_dat_o(), .rd2_read_i(), .rd2_done_i(), .rd2_error_i(), .rd2_ready_o(), .rd2_empty_o(),
- .rd3_dat_o(), .rd3_read_i(), .rd3_done_i(), .rd3_error_i(), .rd3_ready_o(), .rd3_empty_o()
- );
-
-endmodule // buffer_pool_tb
diff --git a/control_lib/cascadefifo.v b/control_lib/cascadefifo.v
deleted file mode 100644
index c1a4ab335..000000000
--- a/control_lib/cascadefifo.v
+++ /dev/null
@@ -1,50 +0,0 @@
-
-
-// This FIFO exists to provide an intermediate point for the data on its
-// long trek from one RAM (in the buffer pool) to another (in the longfifo)
-// The shortfifo is more flexible in its placement since it is based on
-// distributed RAM
-// This one should only be used on transmit side applications. I.e. tx_mac, tx_dsp, etc.
-// Spartan 3's have slow routing....
-// If we REALLY need to, we could also do this on the output side,
-// with for the receive side stuff
-
-module cascadefifo
- #(parameter WIDTH=32, SIZE=9)
- (input clk, input rst,
- input [WIDTH-1:0] datain,
- output [WIDTH-1:0] dataout,
- input read,
- input write,
- input clear,
- output full,
- output empty,
- output [15:0] space,
- output [15:0] occupied);
-
- wire [WIDTH-1:0] data_int;
- wire empty_int, full_int, transfer;
- wire [4:0] short_space, short_occupied;
- wire [15:0] long_space, long_occupied;
-
- shortfifo #(.WIDTH(WIDTH)) shortfifo
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(datain), .write(write), .full(full),
- .dataout(data_int), .read(transfer), .empty(empty_int),
- .space(short_space),.occupied(short_occupied) );
-
- longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(data_int), .write(transfer), .full(full_int),
- .dataout(dataout), .read(read), .empty(empty),
- .space(long_space),.occupied(long_occupied) );
-
- assign transfer = ~empty_int & ~full_int;
-
- assign space = {11'b0,short_space} + long_space;
- assign occupied = {11'b0,short_occupied} + long_occupied;
-
-endmodule // cascadefifo
-
-
-
diff --git a/control_lib/cascadefifo2.v b/control_lib/cascadefifo2.v
deleted file mode 100644
index 984cc46e6..000000000
--- a/control_lib/cascadefifo2.v
+++ /dev/null
@@ -1,56 +0,0 @@
-
-
-// This FIFO exists to provide an intermediate point for the data on its
-// long trek from one RAM (in the buffer pool) to another (in the longfifo)
-// The shortfifo is more flexible in its placement since it is based on
-// distributed RAM
-
-// This one has the shortfifo on both the in and out sides.
-module cascadefifo2
- #(parameter WIDTH=32, SIZE=9)
- (input clk, input rst,
- input [WIDTH-1:0] datain,
- output [WIDTH-1:0] dataout,
- input read,
- input write,
- input clear,
- output full,
- output empty,
- output [15:0] space,
- output [15:0] occupied);
-
- wire [WIDTH-1:0] data_int, data_int2;
- wire empty_int, full_int, transfer;
- wire empty_int2, full_int2, transfer2;
- wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied;
- wire [15:0] l_space, l_occupied;
-
- shortfifo #(.WIDTH(WIDTH)) shortfifo
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(datain), .write(write), .full(full),
- .dataout(data_int), .read(transfer), .empty(empty_int),
- .space(s1_space),.occupied(s1_occupied) );
-
- longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(data_int), .write(transfer), .full(full_int),
- .dataout(data_int2), .read(transfer2), .empty(empty_int2),
- .space(l_space),.occupied(l_occupied) );
-
- shortfifo #(.WIDTH(WIDTH)) shortfifo2
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(data_int2), .write(transfer2), .full(full_int2),
- .dataout(dataout), .read(read), .empty(empty),
- .space(s2_space),.occupied(s2_occupied) );
-
- assign transfer = ~empty_int & ~full_int;
- assign transfer2 = ~empty_int2 & ~full_int2;
-
- assign space = {11'b0,s1_space} + {11'b0,s2_space} + l_space;
- assign occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied;
-
-endmodule // cascadefifo2
-
-
-
-
diff --git a/control_lib/fifo_2clock.v b/control_lib/fifo_2clock.v
deleted file mode 100644
index 6b1eb607e..000000000
--- a/control_lib/fifo_2clock.v
+++ /dev/null
@@ -1,66 +0,0 @@
-
-module fifo_2clock
- #(parameter DWIDTH=32, AWIDTH=9)
- (input wclk, input [DWIDTH-1:0] datain, input write, output full, output reg [AWIDTH-1:0] level_wclk,
- input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output reg [AWIDTH-1:0] level_rclk,
- input arst);
-
- reg [AWIDTH-1:0] wr_addr, rd_addr;
- wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
- wire [AWIDTH-1:0] next_rd_addr;
- wire enb_read;
-
- // Write side management
- wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
- always @(posedge wclk or posedge arst)
- if(arst)
- wr_addr <= 0;
- else if(write)
- wr_addr <= next_wr_addr;
- assign full = (next_wr_addr == rd_addr_wclk);
-
- // RAM for data storage. Data out is registered, complicating the
- // read side logic
- ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
- (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
- .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) );
-
- // Read side management
- reg data_valid;
- assign empty = ~data_valid;
- assign next_rd_addr = rd_addr + data_valid;
- assign enb_read = read | ~data_valid;
-
- always @(posedge rclk or posedge arst)
- if(arst)
- rd_addr <= 0;
- else if(read)
- rd_addr <= rd_addr + 1;
-
- always @(posedge rclk or posedge arst)
- if(arst)
- data_valid <= 0;
- else
- if(read & (next_rd_addr == wr_addr_rclk))
- data_valid <= 0;
- else if(next_rd_addr != wr_addr_rclk)
- data_valid <= 1;
-
- // Send pointers across clock domains via gray code
- gray_send #(.WIDTH(AWIDTH)) send_wr_addr
- (.clk_in(wclk),.addr_in(wr_addr),
- .clk_out(rclk),.addr_out(wr_addr_rclk) );
-
- gray_send #(.WIDTH(AWIDTH)) send_rd_addr
- (.clk_in(rclk),.addr_in(rd_addr),
- .clk_out(wclk),.addr_out(rd_addr_wclk) );
-
- // Generate fullness info, these are approximate and may be delayed
- // and are only for higher-level flow control.
- // Only full and empty are guaranteed exact.
- always @(posedge wclk)
- level_wclk <= wr_addr - rd_addr_wclk;
- always @(posedge rclk)
- level_rclk <= wr_addr_rclk - rd_addr;
-
-endmodule // fifo_2clock
diff --git a/control_lib/fifo_2clock_casc.v b/control_lib/fifo_2clock_casc.v
deleted file mode 100644
index e9b0cfc25..000000000
--- a/control_lib/fifo_2clock_casc.v
+++ /dev/null
@@ -1,31 +0,0 @@
-
-module fifo_2clock_casc
- #(parameter DWIDTH=32, AWIDTH=9)
- (input wclk, input [DWIDTH-1:0] datain, input write, output full, output [AWIDTH-1:0] level_wclk,
- input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output [AWIDTH-1:0] level_rclk,
- input arst);
-
- wire full_int, empty_int, full_int2, empty_int2, transfer, transfer2;
- wire [DWIDTH-1:0] data_int, data_int2;
-
- shortfifo #(.WIDTH(DWIDTH)) shortfifo
- (.clk(wclk), .rst(arst), .clear(0),
- .datain(datain), .write(write), .full(full),
- .dataout(data_int), .read(transfer), .empty(empty_int) );
-
- assign transfer = ~full_int & ~empty_int;
-
- fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
- (.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int), .level_wclk(level_wclk),
- .rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2), .level_rclk(level_rclk),
- .arst(arst) );
-
- assign transfer2 = ~full_int2 & ~empty_int2;
-
- shortfifo #(.WIDTH(DWIDTH)) shortfifo2
- (.clk(rclk), .rst(arst), .clear(0),
- .datain(data_int2), .write(transfer2), .full(full_int2),
- .dataout(dataout), .read(read), .empty(empty) );
-
-endmodule // fifo_2clock_casc
-
diff --git a/control_lib/fifo_reader.v b/control_lib/fifo_reader.v
deleted file mode 100644
index 49d05b1a6..000000000
--- a/control_lib/fifo_reader.v
+++ /dev/null
@@ -1,28 +0,0 @@
-
-module fifo_reader
- #(parameter rate=4)
- (input clk,
- input [31:0] data_in,
- output read_o
- input ready_i,
- input done_i
- );
-
- reg [7:0] state = 0;
-
- always @(posedge clk)
- if(ready)
- if(state == rate)
- state <= 0;
- else
- state <= state + 1;
- else
- state <= 0;
-
- assign read = (state == rate);
-
- initial $monitor(data_in);
-
-endmodule // fifo_reader
-
-
diff --git a/control_lib/fifo_tb.v b/control_lib/fifo_tb.v
index 98fd63f8d..616fe4ee7 100644
--- a/control_lib/fifo_tb.v
+++ b/control_lib/fifo_tb.v
@@ -2,11 +2,11 @@ module fifo_tb();
reg clk, rst;
wire short_full, short_empty, long_full, long_empty;
- wire casc_full, casc_empty, casc2_full, casc2_empty;
+ wire casc2_full, casc2_empty;
reg read, write;
wire [7:0] short_do, long_do;
- wire [7:0] casc_do, casc2_do;
+ wire [7:0] casc2_do;
reg [7:0] di;
reg clear = 0;
@@ -19,10 +19,6 @@ module fifo_tb();
(.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
.read(read),.write(write),.full(long_full),.empty(long_empty));
- cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
- .read(read),.write(write),.full(casc_full),.empty(casc_empty));
-
cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
(.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
.read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
diff --git a/control_lib/fifo_writer.v b/control_lib/fifo_writer.v
deleted file mode 100644
index 064ad3cb9..000000000
--- a/control_lib/fifo_writer.v
+++ /dev/null
@@ -1,31 +0,0 @@
-
-module fifo_writer
- #(parameter rate=4)
- (input clk,
- output [31:0] data_out,
- output write_o,
- input ready_i,
- input done_i
- );
-
- reg [7:0] state = 0;
-
-
- // FIXME change this to write
- always @(posedge clk)
- if(ready)
- if(state == rate)
- state <= 0;
- else
- state <= state + 1;
- else
- state <= 0;
-
- assign read = (state == rate);
-
- initial $monitor(data_in);
-
-endmodule // fifo_writer
-
-
-
diff --git a/control_lib/giantfifo.v b/control_lib/giantfifo.v
deleted file mode 100644
index dba330b8a..000000000
--- a/control_lib/giantfifo.v
+++ /dev/null
@@ -1,209 +0,0 @@
-
-
-
-module giantfifo
- #(parameter WIDTH=36)
- (input clk, input rst,
- input [WIDTH-1:0] datain,
- output [WIDTH-1:0] dataout,
- input read,
- input write,
- input clear,
- output full,
- output empty,
- output [15:0] space,
- output [15:0] occupied,
-
- // External RAM
- inout [17:0] RAM_D,
- output reg [18:0] RAM_A,
- output RAM_CE1n,
- output RAM_CENn,
- output reg RAM_CLK,
- output reg RAM_WEn,
- output RAM_OEn,
- output RAM_LDn
- );
-
- wire [4:0] path1_occ, path2_space;
- wire [35:0] path1_dat, path2_dat;
-
- shortfifo #(.WIDTH(WIDTH)) sf1
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(datain),.write(write),.full(full),
- .dataout(path1_dat),.read(path1_read),.empty(path1_empty),
- .space(),.occupied(path1_occ) );
- wire path1_almost_empty = (path1_occ == 5'd1);
-
- shortfifo #(.WIDTH(WIDTH)) sf2
- (.clk(clk),.rst(rst),.clear(clear),
- .datain(path2_dat),.write(path2_write),.full(path2_full),
- .dataout(dataout),.read(read),.empty(empty),
- .space(path2_space),.occupied() );
- wire path2_almost_full = (path2_space == 5'd1);
-
- assign RAM_CE1n = 1'b0;
- assign RAM_CENn = 1'b0;
- always @(clk)
- RAM_CLK <= #2 clk;
- assign RAM_LDn = 1'b0;
-
- // State machine
- wire write_now, read_now, idle, phase;
- reg ram_full, ram_empty;
-
- reg [17:0] read_ptr, write_ptr;
- reg [2:0] zbt_state;
-
- localparam ZBT_IDLE = 0;
- localparam ZBT_WRITE_UPPER = 2;
- localparam ZBT_WRITE_LOWER = 3;
- localparam ZBT_READ_UPPER = 4;
- localparam ZBT_READ_LOWER = 5;
-
- wire can_write = ~ram_full & ~path1_empty;
- wire can_write_chain = can_write & ~path1_almost_empty;
-
- wire can_read = ~ram_empty & ~path2_full;
- wire can_read_chain = can_read & ~path2_almost_full;
-
- assign phase = zbt_state[0];
-
- reg [17:0] ram_occupied;
- wire ram_almost_empty = (write_ptr == (read_ptr+1'b1));
- wire ram_almost_full = ((write_ptr+1'b1) == read_ptr);
-
- always @(posedge clk)
- if(rst | clear)
- begin
- zbt_state <= ZBT_IDLE;
- write_ptr <= 0;
- read_ptr <= 0;
- ram_full <= 0;
- ram_empty <= 1;
- ram_occupied <= 0;
- end
- else
- case(zbt_state)
- ZBT_IDLE :
- if(can_read)
- zbt_state <= ZBT_READ_UPPER;
- else if(can_write)
- zbt_state <= ZBT_WRITE_UPPER;
-
- ZBT_WRITE_UPPER :
- begin
- zbt_state <= ZBT_WRITE_LOWER;
- ram_occupied <= ram_occupied + 1;
- ram_empty <= 0;
- if(ram_occupied == 18'd10)
- ram_full <= 1;
- end
- ZBT_WRITE_LOWER :
- begin
- write_ptr <= write_ptr + 1;
- if(can_read_chain)
- zbt_state <= ZBT_READ_UPPER;
- else if(can_write_chain)
- zbt_state <= ZBT_WRITE_UPPER;
- else
- zbt_state <= ZBT_IDLE;
- end
- ZBT_READ_UPPER :
- begin
- zbt_state <= ZBT_READ_LOWER;
- ram_occupied <= ram_occupied - 1;
- ram_full <= 0;
- if(ram_occupied == 18'd1)
- ram_empty <= 1;
- end
- ZBT_READ_LOWER :
- begin
- read_ptr <= read_ptr + 1;
- if(can_read_chain)
- zbt_state <= ZBT_READ_UPPER;
- else if(can_write_chain)
- zbt_state <= ZBT_WRITE_UPPER;
- else
- zbt_state <= ZBT_IDLE;
- end
- default :
- zbt_state <= ZBT_IDLE;
- endcase // case(zbt_state)
-
- // Need to generate RAM_WEn, RAM_OEn, RAM_D, RAM_A;
- assign path1_read = (zbt_state == ZBT_WRITE_LOWER);
- reg path2_write, delayed_read_upper, delayed_read_lower, delayed_write;
-
- always @(posedge clk)
- if(delayed_read_upper)
- path2_dat[35:18] <= RAM_D;
- always @(posedge clk)
- if(delayed_read_lower)
- path2_dat[17:0] <= RAM_D;
-
- always @(posedge clk)
- if(rst)
- begin
- delayed_read_upper <= 0;
- delayed_read_lower <= 0;
- path2_write <= 0;
- end
- else
- begin
- delayed_read_upper <= (zbt_state == ZBT_READ_LOWER);
- delayed_read_lower <= delayed_read_upper;
- path2_write <= delayed_read_lower;
- end
-
- reg [17:0] RAM_D_pre2, RAM_D_pre1, RAM_D_out;
-
- always @(posedge clk)
- RAM_D_pre2 <= phase ? path1_dat[17:0] : path1_dat[35:18];
-
- always @(posedge clk) RAM_D_pre1 <= RAM_D_pre2;
- always @(posedge clk) RAM_D_out <= RAM_D_pre1;
- reg wr_del_1, wr_del_2;
- always @(posedge clk)
- if(rst)
- begin
- wr_del_1 <= 0;
- wr_del_2 <= 0;
- delayed_write <= 0;
- end
- else
- begin
- delayed_write <= wr_del_2;
- wr_del_2 <= wr_del_1;
- wr_del_1 <= write_now;
- end
-
- reg delayed_read, rd_del_1, rd_del_2;
- always @(posedge clk)
- if(rst)
- begin
- rd_del_1 <= 0;
- rd_del_2 <= 0;
- delayed_read <= 0;
- end
- else
- begin
- delayed_read <= rd_del_2;
- rd_del_2 <= rd_del_1;
- rd_del_1 <= read_now;
- end
-
- assign RAM_D = delayed_write ? RAM_D_out : 18'bzzzzzzzzzzzzzzzzzz;
- assign write_now = (zbt_state == ZBT_WRITE_UPPER) || (zbt_state == ZBT_WRITE_LOWER);
- assign read_now = (zbt_state == ZBT_READ_UPPER) || (zbt_state == ZBT_READ_LOWER);
-
- always @(posedge clk)
- RAM_A <= write_now ? {write_ptr,phase} : {read_ptr,phase};
-
- always @(posedge clk)
- RAM_WEn <= ~write_now;
-
- assign RAM_OEn = ~delayed_read;
- assign RAM_OEn = 0;
-
-endmodule // giantfifo
diff --git a/control_lib/giantfifo_tb.v b/control_lib/giantfifo_tb.v
deleted file mode 100644
index 87ecd97ae..000000000
--- a/control_lib/giantfifo_tb.v
+++ /dev/null
@@ -1,173 +0,0 @@
-module fifo_tb();
-
- localparam WIDTH = 36;
- reg clk, rst;
- wire short_full, short_empty, long_full, long_empty, giant_full, giant_empty;
- wire casc_full, casc_empty, casc2_full, casc2_empty;
- reg read, write;
-
- wire [WIDTH-1:0] short_do, long_do, casc_do, casc2_do, giant_do;
- reg [WIDTH-1:0] di;
-
- reg clear = 0;
-
- shortfifo #(.WIDTH(WIDTH)) shortfifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
- .read(read),.write(write),.full(short_full),.empty(short_empty));
-
- longfifo #(.WIDTH(WIDTH), .SIZE(4)) longfifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
- .read(read),.write(write),.full(long_full),.empty(long_empty));
-
- cascadefifo #(.WIDTH(WIDTH), .SIZE(4)) cascadefifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
- .read(read),.write(write),.full(casc_full),.empty(casc_empty));
-
- cascadefifo2 #(.WIDTH(WIDTH), .SIZE(4)) cascadefifo2
- (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
- .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
-
- wire [17:0] RAM_D;
- wire [18:0] RAM_A;
- wire RAM_CLK, RAM_WEn, RAM_LDn, RAM_CE1n, RAM_OEn, RAM_CENn;
-
- giantfifo #(.WIDTH(WIDTH)) giantfifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(giant_do),.clear(clear),
- .read(read),.write(write),.full(giant_full),.empty(giant_empty),
- .RAM_D(RAM_D),.RAM_A(RAM_A),.RAM_CE1n(RAM_CE1n),.RAM_CENn(RAM_CENn),
- .RAM_CLK(RAM_CLK),.RAM_WEn(RAM_WEn),.RAM_OEn(RAM_OEn),.RAM_LDn(RAM_LDn)
- );
-
- wire MODE = 1'b0;
- cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A),
- .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn),
- .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0),
- .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(MODE)
- );
-
- initial rst = 1;
- initial #1000 rst = 0;
- initial clk = 0;
- always #50 clk = ~clk;
-
- initial di = 36'h300AE;
- initial read = 0;
- initial write = 0;
-
- always @(posedge clk)
- if(write)
- di <= di + 1;
-
- always @(posedge clk)
- begin
- if(short_full != long_full)
- $display("Error: FULL mismatch");
- if(short_empty != long_empty)
- $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)");
- if(read & (short_do != long_do))
- $display("Error: DATA mismatch");
- end
-
- initial $dumpfile("giantfifo_tb.vcd");
- initial $dumpvars(0,fifo_tb);
-
- initial
- begin
- @(negedge rst);
- @(posedge clk);
- repeat (10)
- @(posedge clk);
- write <= 1;
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- read <= 1;
- @(posedge clk);
- read <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
-
- repeat(10)
- begin
- write <= 1;
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- read <= 1;
- @(posedge clk);
- read <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- end // repeat (10)
-
- write <= 1;
- repeat (4)
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- read <= 1;
- repeat (4)
- @(posedge clk);
- read <= 0;
- @(posedge clk);
-
-
- write <= 1;
- repeat (4)
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- repeat (4)
- begin
- read <= 1;
- @(posedge clk);
- read <= 0;
- @(posedge clk);
- end
-
- write <= 1;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- read <= 1;
- repeat (5)
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- @(posedge clk);
- read <= 0;
- @(posedge clk);
-
- write <= 1;
- repeat (16)
- @(posedge clk);
- write <= 0;
- @(posedge clk);
-
- read <= 1;
- repeat (16)
- @(posedge clk);
- read <= 0;
- @(posedge clk);
-
- repeat (10)
- @(posedge clk);
- $finish;
- end
-endmodule // longfifo_tb
diff --git a/control_lib/newfifo/.gitignore b/control_lib/newfifo/.gitignore
new file mode 100644
index 000000000..cba7efc8e
--- /dev/null
+++ b/control_lib/newfifo/.gitignore
@@ -0,0 +1 @@
+a.out
diff --git a/control_lib/newfifo/fifo18_to_ll8.v b/control_lib/newfifo/fifo18_to_ll8.v
deleted file mode 100644
index 4653244ef..000000000
--- a/control_lib/newfifo/fifo18_to_ll8.v
+++ /dev/null
@@ -1,58 +0,0 @@
-
-module fifo18_to_ll8
- (input clk, input reset, input clear,
- input [35:0] f18_data,
- input f18_src_rdy_i,
- output f18_dst_rdy_o,
-
- output reg [7:0] ll_data,
- output ll_sof_n,
- output ll_eof_n,
- output ll_src_rdy_n,
- input ll_dst_rdy_n);
-
- wire ll_sof, ll_eof, ll_src_rdy;
- assign ll_sof_n = ~ll_sof;
- assign ll_eof_n = ~ll_eof;
- assign ll_src_rdy_n = ~ll_src_rdy;
- wire ll_dst_rdy = ~ll_dst_rdy_n;
-
- wire f18_sof = f18_data[32];
- wire f18_eof = f18_data[33];
- wire f18_occ = f18_data[35:34];
- wire advance, end_early;
- reg [1:0] state;
- assign debug = {29'b0,state};
-
- always @(posedge clk)
- if(reset)
- state <= 0;
- else
- if(advance)
- if(ll_eof)
- state <= 0;
- else
- state <= state + 1;
-
- always @*
- case(state)
- 0 : ll_data = f18_data[31:24];
- 1 : ll_data = f18_data[23:16];
- 2 : ll_data = f18_data[15:8];
- 3 : ll_data = f18_data[7:0];
- default : ll_data = f18_data[31:24];
- endcase // case (state)
-
- assign ll_sof = (state==0) & f18_sof;
- assign ll_eof = f18_eof & (((state==0)&(f18_occ==1)) |
- ((state==1)&(f18_occ==2)) |
- ((state==2)&(f18_occ==3)) |
- (state==3));
-
- assign ll_src_rdy = f18_src_rdy_i;
-
- assign advance = ll_src_rdy & ll_dst_rdy;
- assign f18_dst_rdy_o = advance & ((state==3)|ll_eof);
- assign debug = state;
-
-endmodule // ll8_to_fifo36
diff --git a/control_lib/newfifo/fifo36_to_ll8.v b/control_lib/newfifo/fifo36_to_ll8.v
index 1befb9e6e..0dee1dfc6 100644
--- a/control_lib/newfifo/fifo36_to_ll8.v
+++ b/control_lib/newfifo/fifo36_to_ll8.v
@@ -1,6 +1,6 @@
module fifo36_to_ll8
- (input clk, reset,
+ (input clk, input reset, input clear,
input [35:0] f36_data,
input f36_src_rdy_i,
output f36_dst_rdy_o,
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 6b1eb607e..07ae090f2 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -1,9 +1,58 @@
+// FIXME ignores the AWIDTH (fifo size) parameter
+
module fifo_2clock
- #(parameter DWIDTH=32, AWIDTH=9)
- (input wclk, input [DWIDTH-1:0] datain, input write, output full, output reg [AWIDTH-1:0] level_wclk,
- input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output reg [AWIDTH-1:0] level_rclk,
- input arst);
+ #(parameter WIDTH=36, SIZE=6)
+ (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+ input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+ input arst);
+
+ wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels
+ wire full, empty, write, read;
+
+ assign dst_rdy_o = ~full;
+ assign src_rdy_o = ~empty;
+ assign write = src_rdy_i & dst_rdy_o;
+ assign read = src_rdy_o & dst_rdy_i;
+
+ generate
+ if(WIDTH==36)
+ if(SIZE==9)
+ fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if(SIZE==11)
+ fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if(SIZE==6)
+ fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else
+ fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if((WIDTH==19)|(WIDTH==18))
+ if(SIZE==4)
+ fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ endgenerate
+
+ assign occupied = {{(16-SIZE-1){1'b0}},level_rclk};
+ assign space = ((1<<SIZE)+1)-level_wclk;
+
+endmodule // fifo_2clock
+
+/*
+`else
+ // ISE sucks, so the following doesn't work properly
reg [AWIDTH-1:0] wr_addr, rd_addr;
wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
@@ -62,5 +111,7 @@ module fifo_2clock
level_wclk <= wr_addr - rd_addr_wclk;
always @(posedge rclk)
level_rclk <= wr_addr_rclk - rd_addr;
-
+`endif
endmodule // fifo_2clock
+
+*/
diff --git a/control_lib/newfifo/fifo_2clock_casc.v b/control_lib/newfifo/fifo_2clock_casc.v
deleted file mode 100644
index e9b0cfc25..000000000
--- a/control_lib/newfifo/fifo_2clock_casc.v
+++ /dev/null
@@ -1,31 +0,0 @@
-
-module fifo_2clock_casc
- #(parameter DWIDTH=32, AWIDTH=9)
- (input wclk, input [DWIDTH-1:0] datain, input write, output full, output [AWIDTH-1:0] level_wclk,
- input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output [AWIDTH-1:0] level_rclk,
- input arst);
-
- wire full_int, empty_int, full_int2, empty_int2, transfer, transfer2;
- wire [DWIDTH-1:0] data_int, data_int2;
-
- shortfifo #(.WIDTH(DWIDTH)) shortfifo
- (.clk(wclk), .rst(arst), .clear(0),
- .datain(datain), .write(write), .full(full),
- .dataout(data_int), .read(transfer), .empty(empty_int) );
-
- assign transfer = ~full_int & ~empty_int;
-
- fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
- (.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int), .level_wclk(level_wclk),
- .rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2), .level_rclk(level_rclk),
- .arst(arst) );
-
- assign transfer2 = ~full_int2 & ~empty_int2;
-
- shortfifo #(.WIDTH(DWIDTH)) shortfifo2
- (.clk(rclk), .rst(arst), .clear(0),
- .datain(data_int2), .write(transfer2), .full(full_int2),
- .dataout(dataout), .read(read), .empty(empty) );
-
-endmodule // fifo_2clock_casc
-
diff --git a/control_lib/newfifo/fifo_2clock_cascade.v b/control_lib/newfifo/fifo_2clock_cascade.v
new file mode 100644
index 000000000..5ce726977
--- /dev/null
+++ b/control_lib/newfifo/fifo_2clock_cascade.v
@@ -0,0 +1,35 @@
+
+module fifo_2clock_cascade
+ #(parameter WIDTH=32, SIZE=9)
+ (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+ input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+ input arst);
+
+ wire [WIDTH-1:0] data_int1, data_int2;
+ wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+ wire [SIZE-1:0] level_wclk, level_rclk;
+ wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied;
+ wire [15:0] l_space, l_occupied;
+
+ fifo_short #(.WIDTH(WIDTH)) shortfifo
+ (.clk(wclk), .reset(arst), .clear(0),
+ .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
+ .space(s1_space), .occupied(s1_occupied) );
+
+ fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
+ (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
+ .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
+ .arst(arst) );
+
+ fifo_short #(.WIDTH(WIDTH)) shortfifo2
+ (.clk(rclk), .reset(arst), .clear(0),
+ .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
+ .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+ .space(s2_space), .occupied(s2_occupied));
+
+ // Be conservative -- Only advertise space from input side of fifo, occupied from output side
+ assign space = {11'b0,s1_space} + l_space;
+ assign occupied = {11'b0,s2_occupied} + l_occupied;
+
+endmodule // fifo_2clock_cascade
diff --git a/control_lib/newfifo/fifo_new_tb.v b/control_lib/newfifo/fifo_new_tb.v
deleted file mode 100644
index f561df7fa..000000000
--- a/control_lib/newfifo/fifo_new_tb.v
+++ /dev/null
@@ -1,158 +0,0 @@
-module fifo_new_tb();
-
- reg clk = 0;
- reg rst = 1;
- reg clear = 0;
- initial #1000 rst = 0;
- always #50 clk = ~clk;
-
- reg [31:0] f36_data = 0;
- reg [1:0] f36_occ = 0;
- reg f36_sof = 0, f36_eof = 0;
-
- wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
- reg src_rdy_f36i = 0;
- wire dst_rdy_f36i;
-
- wire [35:0] f36_out, f36_out2;
- wire src_rdy_f36o;
- reg dst_rdy_f36o = 0;
-
- //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
- //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
-
- wire i1_sr, i1_dr;
- wire i2_sr, i2_dr;
- wire i3_sr, i3_dr;
- reg i4_dr = 0;
- wire i4_sr;
-
- wire [35:0] i1, i4;
- wire [18:0] i2, i3;
-
- wire [7:0] ll_data;
- wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
-
- fifo_short #(.WIDTH(36)) fifo_short1
- (.clk(clk),.reset(rst),.clear(clear),
- .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
- .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
-
- fifo36_to_fifo19 fifo36_to_fifo19
- (.clk(clk),.reset(rst),.clear(clear),
- .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
- .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
-
- fifo19_to_ll8 fifo19_to_ll8
- (.clk(clk),.reset(rst),.clear(clear),
- .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
- .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
- .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
-
- ll8_to_fifo19 ll8_to_fifo19
- (.clk(clk),.reset(rst),.clear(clear),
- .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
- .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
- .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
-
- fifo19_to_fifo36 fifo19_to_fifo36
- (.clk(clk),.reset(rst),.clear(clear),
- .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
- .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
-
- task ReadFromFIFO36;
- begin
- $display("Read from FIFO36");
- #1 i4_dr <= 1;
- while(1)
- begin
- while(~i4_sr)
- @(posedge clk);
- $display("Read: %h",i4);
- @(posedge clk);
- end
- end
- endtask // ReadFromFIFO36
-
- reg [15:0] count;
- task PutPacketInFIFO36;
- input [31:0] data_start;
- input [31:0] data_len;
- begin
- count <= 4;
- src_rdy_f36i <= 1;
- f36_data <= data_start;
- f36_sof <= 1;
- f36_eof <= 0;
- f36_occ <= 0;
-
- $display("Put Packet in FIFO36");
- while(~dst_rdy_f36i)
- @(posedge clk);
- @(posedge clk);
- $display("PPI_FIFO36: Entered First Line");
- f36_sof <= 0;
- while(count+4 < data_len)
- begin
- f36_data <= f36_data + 32'h01010101;
- count <= count + 4;
- while(~dst_rdy_f36i)
- @(posedge clk);
- @(posedge clk);
- $display("PPI_FIFO36: Entered New Line");
- end
- f36_data <= f36_data + 32'h01010101;
- f36_eof <= 1;
- if(count + 4 == data_len)
- f36_occ <= 0;
- else if(count + 3 == data_len)
- f36_occ <= 3;
- else if(count + 2 == data_len)
- f36_occ <= 2;
- else
- f36_occ <= 1;
- while(~dst_rdy_f36i)
- @(posedge clk);
- @(posedge clk);
- f36_occ <= 0;
- f36_eof <= 0;
- f36_data <= 0;
- src_rdy_f36i <= 0;
- $display("PPI_FIFO36: Entered Last Line");
- end
- endtask // PutPacketInFIFO36
-
- initial $dumpfile("fifo_new_tb.vcd");
- initial $dumpvars(0,fifo_new_tb);
-
- initial
- begin
- @(negedge rst);
- //#10000;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- ReadFromFIFO36;
- end
-
- initial
- begin
- @(negedge rst);
- @(posedge clk);
- @(posedge clk);
- PutPacketInFIFO36(32'hA0B0C0D0,12);
- @(posedge clk);
- @(posedge clk);
- #10000;
- @(posedge clk);
- PutPacketInFIFO36(32'hE0F0A0B0,36);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- end
-
- initial #20000 $finish;
-endmodule // longfifo_tb
diff --git a/control_lib/newfifo/fifo_tb.v b/control_lib/newfifo/fifo_tb.v
index 98fd63f8d..f561df7fa 100644
--- a/control_lib/newfifo/fifo_tb.v
+++ b/control_lib/newfifo/fifo_tb.v
@@ -1,155 +1,158 @@
-module fifo_tb();
+module fifo_new_tb();
- reg clk, rst;
- wire short_full, short_empty, long_full, long_empty;
- wire casc_full, casc_empty, casc2_full, casc2_empty;
- reg read, write;
-
- wire [7:0] short_do, long_do;
- wire [7:0] casc_do, casc2_do;
- reg [7:0] di;
-
- reg clear = 0;
-
- shortfifo #(.WIDTH(8)) shortfifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
- .read(read),.write(write),.full(short_full),.empty(short_empty));
+ reg clk = 0;
+ reg rst = 1;
+ reg clear = 0;
+ initial #1000 rst = 0;
+ always #50 clk = ~clk;
- longfifo #(.WIDTH(8), .SIZE(4)) longfifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
- .read(read),.write(write),.full(long_full),.empty(long_empty));
+ reg [31:0] f36_data = 0;
+ reg [1:0] f36_occ = 0;
+ reg f36_sof = 0, f36_eof = 0;
- cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
- .read(read),.write(write),.full(casc_full),.empty(casc_empty));
+ wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+ reg src_rdy_f36i = 0;
+ wire dst_rdy_f36i;
+
+ wire [35:0] f36_out, f36_out2;
+ wire src_rdy_f36o;
+ reg dst_rdy_f36o = 0;
- cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
- (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
- .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
+ //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+ //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+
+ wire i1_sr, i1_dr;
+ wire i2_sr, i2_dr;
+ wire i3_sr, i3_dr;
+ reg i4_dr = 0;
+ wire i4_sr;
+
+ wire [35:0] i1, i4;
+ wire [18:0] i2, i3;
- initial rst = 1;
- initial #1000 rst = 0;
- initial clk = 0;
- always #50 clk = ~clk;
+ wire [7:0] ll_data;
+ wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
- initial di = 8'hAE;
- initial read = 0;
- initial write = 0;
+ fifo_short #(.WIDTH(36)) fifo_short1
+ (.clk(clk),.reset(rst),.clear(clear),
+ .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+ .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
- always @(posedge clk)
- if(write)
- di <= di + 1;
-
- always @(posedge clk)
- begin
- if(short_full != long_full)
- $display("Error: FULL mismatch");
- if(short_empty != long_empty)
- $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)");
- if(read & (short_do != long_do))
- $display("Error: DATA mismatch");
- end
+ fifo36_to_fifo19 fifo36_to_fifo19
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
+ .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
+
+ fifo19_to_ll8 fifo19_to_ll8
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
+ .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+ .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
+
+ ll8_to_fifo19 ll8_to_fifo19
+ (.clk(clk),.reset(rst),.clear(clear),
+ .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+ .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
+ .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
+
+ fifo19_to_fifo36 fifo19_to_fifo36
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
+ .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
+
+ task ReadFromFIFO36;
+ begin
+ $display("Read from FIFO36");
+ #1 i4_dr <= 1;
+ while(1)
+ begin
+ while(~i4_sr)
+ @(posedge clk);
+ $display("Read: %h",i4);
+ @(posedge clk);
+ end
+ end
+ endtask // ReadFromFIFO36
+
+ reg [15:0] count;
+ task PutPacketInFIFO36;
+ input [31:0] data_start;
+ input [31:0] data_len;
+ begin
+ count <= 4;
+ src_rdy_f36i <= 1;
+ f36_data <= data_start;
+ f36_sof <= 1;
+ f36_eof <= 0;
+ f36_occ <= 0;
+
+ $display("Put Packet in FIFO36");
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ $display("PPI_FIFO36: Entered First Line");
+ f36_sof <= 0;
+ while(count+4 < data_len)
+ begin
+ f36_data <= f36_data + 32'h01010101;
+ count <= count + 4;
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ $display("PPI_FIFO36: Entered New Line");
+ end
+ f36_data <= f36_data + 32'h01010101;
+ f36_eof <= 1;
+ if(count + 4 == data_len)
+ f36_occ <= 0;
+ else if(count + 3 == data_len)
+ f36_occ <= 3;
+ else if(count + 2 == data_len)
+ f36_occ <= 2;
+ else
+ f36_occ <= 1;
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ f36_occ <= 0;
+ f36_eof <= 0;
+ f36_data <= 0;
+ src_rdy_f36i <= 0;
+ $display("PPI_FIFO36: Entered Last Line");
+ end
+ endtask // PutPacketInFIFO36
- initial $dumpfile("fifo_tb.vcd");
- initial $dumpvars(0,fifo_tb);
+ initial $dumpfile("fifo_new_tb.vcd");
+ initial $dumpvars(0,fifo_new_tb);
initial
begin
@(negedge rst);
- @(posedge clk);
- repeat (10)
- @(posedge clk);
- write <= 1;
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- @(posedge clk);
+ //#10000;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
+ ReadFromFIFO36;
+ end
+
+ initial
+ begin
+ @(negedge rst);
@(posedge clk);
@(posedge clk);
- read <= 1;
- @(posedge clk);
- read <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
-
- repeat(10)
- begin
- write <= 1;
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- read <= 1;
- @(posedge clk);
- read <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- end // repeat (10)
-
- write <= 1;
- repeat (4)
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- read <= 1;
- repeat (4)
- @(posedge clk);
- read <= 0;
- @(posedge clk);
-
-
- write <= 1;
- repeat (4)
- @(posedge clk);
- write <= 0;
+ PutPacketInFIFO36(32'hA0B0C0D0,12);
@(posedge clk);
- repeat (4)
- begin
- read <= 1;
- @(posedge clk);
- read <= 0;
- @(posedge clk);
- end
-
- write <= 1;
@(posedge clk);
+ #10000;
@(posedge clk);
+ PutPacketInFIFO36(32'hE0F0A0B0,36);
@(posedge clk);
@(posedge clk);
- read <= 1;
- repeat (5)
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- @(posedge clk);
- read <= 0;
@(posedge clk);
-
- write <= 1;
- repeat (16)
- @(posedge clk);
- write <= 0;
@(posedge clk);
-
- read <= 1;
- repeat (16)
- @(posedge clk);
- read <= 0;
@(posedge clk);
-
- repeat (10)
- @(posedge clk);
- $finish;
end
+
+ initial #20000 $finish;
endmodule // longfifo_tb
diff --git a/control_lib/newfifo/ll8_shortfifo.v b/control_lib/newfifo/ll8_shortfifo.v
new file mode 100644
index 000000000..39ada9a4f
--- /dev/null
+++ b/control_lib/newfifo/ll8_shortfifo.v
@@ -0,0 +1,13 @@
+
+
+module ll8_shortfifo
+ (input clk, input reset, input clear,
+ input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o,
+ output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i);
+
+ fifo_short #(.WIDTH(11)) fifo_short
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+
+endmodule // ll8_shortfifo
diff --git a/control_lib/wb_1master.v b/control_lib/wb_1master.v
index e56ba1fb2..fb313efae 100644
--- a/control_lib/wb_1master.v
+++ b/control_lib/wb_1master.v
@@ -38,26 +38,40 @@
// Up to 8 slaves share a Wishbone Bus connection to 1 master
module wb_1master
- #(parameter s0_addr_w = 4, // slave 0 address decode width
- parameter s0_addr = 4'h0, // slave 0 address
- parameter s1_addr_w = 4 , // slave 1 address decode width
- parameter s1_addr = 4'h1, // slave 1 address
- parameter s215_addr_w = 8 , // slave 2 to slave 7 address decode width
- parameter s2_addr = 8'h92, // slave 2 address
- parameter s3_addr = 8'h93, // slave 3 address
- parameter s4_addr = 8'h94, // slave 4 address
- parameter s5_addr = 8'h95, // slave 5 address
- parameter s6_addr = 8'h96, // slave 6 address
- parameter s7_addr = 8'h97, // slave 7 address
- parameter s8_addr = 8'h98, // slave 7 address
- parameter s9_addr = 8'h99, // slave 7 address
- parameter s10_addr = 8'h9a, // slave 7 address
- parameter s11_addr = 8'h9b, // slave 7 address
- parameter s12_addr = 8'h9c, // slave 7 address
- parameter s13_addr = 8'h9d, // slave 7 address
- parameter s14_addr = 8'h9e, // slave 7 address
- parameter s15_addr = 8'h9f, // slave 7 address
-
+ #(parameter decode_w = 8, // address decode width
+ parameter s0_addr = 8'h0, // slave 0 address
+ parameter s0_mask = 8'h0, // slave 0 don't cares
+ parameter s1_addr = 8'h0, // slave 1 address
+ parameter s1_mask = 8'h0, // slave 1 don't cares
+ parameter s2_addr = 8'h0, // slave 2 address
+ parameter s2_mask = 8'h0, // slave 2 don't cares
+ parameter s3_addr = 8'h0, // slave 3 address
+ parameter s3_mask = 8'h0, // slave 3 don't cares
+ parameter s4_addr = 8'h0, // slave 4 address
+ parameter s4_mask = 8'h0, // slave 4 don't cares
+ parameter s5_addr = 8'h0, // slave 5 address
+ parameter s5_mask = 8'h0, // slave 5 don't cares
+ parameter s6_addr = 8'h0, // slave 6 address
+ parameter s6_mask = 8'h0, // slave 6 don't cares
+ parameter s7_addr = 8'h0, // slave 7 address
+ parameter s7_mask = 8'h0, // slave 7 don't cares
+ parameter s8_addr = 8'h0, // slave 8 address
+ parameter s8_mask = 8'h0, // slave 8 don't cares
+ parameter s9_addr = 8'h0, // slave 9 address
+ parameter s9_mask = 8'h0, // slave 9 don't cares
+ parameter sa_addr = 8'h0, // slave a address
+ parameter sa_mask = 8'h0, // slave a don't cares
+ parameter sb_addr = 8'h0, // slave b address
+ parameter sb_mask = 8'h0, // slave b don't cares
+ parameter sc_addr = 8'h0, // slave c address
+ parameter sc_mask = 8'h0, // slave c don't cares
+ parameter sd_addr = 8'h0, // slave d address
+ parameter sd_mask = 8'h0, // slave d don't cares
+ parameter se_addr = 8'h0, // slave e address
+ parameter se_mask = 8'h0, // slave e don't cares
+ parameter sf_addr = 8'h0, // slave f address
+ parameter sf_mask = 8'h0, // slave f don't cares
+
parameter dw = 32, // Data bus Width
parameter aw = 32, // Address bus Width
parameter sw = 4) // Number of Select Lines
@@ -188,71 +202,71 @@
input s9_err_i,
input s9_rty_i,
- input [dw-1:0] s10_dat_i,
- output [dw-1:0] s10_dat_o,
- output [aw-1:0] s10_adr_o,
- output [sw-1:0] s10_sel_o,
- output s10_we_o,
- output s10_cyc_o,
- output s10_stb_o,
- input s10_ack_i,
- input s10_err_i,
- input s10_rty_i,
+ input [dw-1:0] sa_dat_i,
+ output [dw-1:0] sa_dat_o,
+ output [aw-1:0] sa_adr_o,
+ output [sw-1:0] sa_sel_o,
+ output sa_we_o,
+ output sa_cyc_o,
+ output sa_stb_o,
+ input sa_ack_i,
+ input sa_err_i,
+ input sa_rty_i,
- input [dw-1:0] s11_dat_i,
- output [dw-1:0] s11_dat_o,
- output [aw-1:0] s11_adr_o,
- output [sw-1:0] s11_sel_o,
- output s11_we_o,
- output s11_cyc_o,
- output s11_stb_o,
- input s11_ack_i,
- input s11_err_i,
- input s11_rty_i,
+ input [dw-1:0] sb_dat_i,
+ output [dw-1:0] sb_dat_o,
+ output [aw-1:0] sb_adr_o,
+ output [sw-1:0] sb_sel_o,
+ output sb_we_o,
+ output sb_cyc_o,
+ output sb_stb_o,
+ input sb_ack_i,
+ input sb_err_i,
+ input sb_rty_i,
- input [dw-1:0] s12_dat_i,
- output [dw-1:0] s12_dat_o,
- output [aw-1:0] s12_adr_o,
- output [sw-1:0] s12_sel_o,
- output s12_we_o,
- output s12_cyc_o,
- output s12_stb_o,
- input s12_ack_i,
- input s12_err_i,
- input s12_rty_i,
+ input [dw-1:0] sc_dat_i,
+ output [dw-1:0] sc_dat_o,
+ output [aw-1:0] sc_adr_o,
+ output [sw-1:0] sc_sel_o,
+ output sc_we_o,
+ output sc_cyc_o,
+ output sc_stb_o,
+ input sc_ack_i,
+ input sc_err_i,
+ input sc_rty_i,
- input [dw-1:0] s13_dat_i,
- output [dw-1:0] s13_dat_o,
- output [aw-1:0] s13_adr_o,
- output [sw-1:0] s13_sel_o,
- output s13_we_o,
- output s13_cyc_o,
- output s13_stb_o,
- input s13_ack_i,
- input s13_err_i,
- input s13_rty_i,
+ input [dw-1:0] sd_dat_i,
+ output [dw-1:0] sd_dat_o,
+ output [aw-1:0] sd_adr_o,
+ output [sw-1:0] sd_sel_o,
+ output sd_we_o,
+ output sd_cyc_o,
+ output sd_stb_o,
+ input sd_ack_i,
+ input sd_err_i,
+ input sd_rty_i,
- input [dw-1:0] s14_dat_i,
- output [dw-1:0] s14_dat_o,
- output [aw-1:0] s14_adr_o,
- output [sw-1:0] s14_sel_o,
- output s14_we_o,
- output s14_cyc_o,
- output s14_stb_o,
- input s14_ack_i,
- input s14_err_i,
- input s14_rty_i,
+ input [dw-1:0] se_dat_i,
+ output [dw-1:0] se_dat_o,
+ output [aw-1:0] se_adr_o,
+ output [sw-1:0] se_sel_o,
+ output se_we_o,
+ output se_cyc_o,
+ output se_stb_o,
+ input se_ack_i,
+ input se_err_i,
+ input se_rty_i,
- input [dw-1:0] s15_dat_i,
- output [dw-1:0] s15_dat_o,
- output [aw-1:0] s15_adr_o,
- output [sw-1:0] s15_sel_o,
- output s15_we_o,
- output s15_cyc_o,
- output s15_stb_o,
- input s15_ack_i,
- input s15_err_i,
- input s15_rty_i
+ input [dw-1:0] sf_dat_i,
+ output [dw-1:0] sf_dat_o,
+ output [aw-1:0] sf_adr_o,
+ output [sw-1:0] sf_sel_o,
+ output sf_we_o,
+ output sf_cyc_o,
+ output sf_stb_o,
+ input sf_ack_i,
+ input sf_err_i,
+ input sf_rty_i
);
// ////////////////////////////////////////////////////////////////
@@ -278,22 +292,22 @@
128 : i_dat_s <= s7_dat_i;
256 : i_dat_s <= s8_dat_i;
512 : i_dat_s <= s9_dat_i;
- 1024 : i_dat_s <= s10_dat_i;
- 2048 : i_dat_s <= s11_dat_i;
- 4096 : i_dat_s <= s12_dat_i;
- 8192 : i_dat_s <= s13_dat_i;
- 16384 : i_dat_s <= s14_dat_i;
- 32768 : i_dat_s <= s15_dat_i;
+ 1024 : i_dat_s <= sa_dat_i;
+ 2048 : i_dat_s <= sb_dat_i;
+ 4096 : i_dat_s <= sc_dat_i;
+ 8192 : i_dat_s <= sd_dat_i;
+ 16384 : i_dat_s <= se_dat_i;
+ 32768 : i_dat_s <= sf_dat_i;
default : i_dat_s <= s0_dat_i;
endcase // case(ssel_dec)
assign {m0_ack_o, m0_err_o, m0_rty_o}
= {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i |
- s8_ack_i | s9_ack_i | s10_ack_i | s11_ack_i | s12_ack_i | s13_ack_i | s14_ack_i | s15_ack_i ,
+ s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i ,
s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i |
- s8_err_i | s9_err_i | s10_err_i | s11_err_i | s12_err_i | s13_err_i | s14_err_i | s15_err_i ,
+ s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i ,
s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i |
- s8_rty_i | s9_rty_i | s10_rty_i | s11_rty_i | s12_rty_i | s13_rty_i | s14_rty_i | s15_rty_i };
+ s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i };
// Slave output interfaces
assign s0_adr_o = m0_adr_i;
@@ -366,65 +380,85 @@
assign s9_cyc_o = m0_cyc_i;
assign s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9];
- assign s10_adr_o = m0_adr_i;
- assign s10_sel_o = m0_sel_i;
- assign s10_dat_o = m0_dat_i;
- assign s10_we_o = m0_we_i;
- assign s10_cyc_o = m0_cyc_i;
- assign s10_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];
+ assign sa_adr_o = m0_adr_i;
+ assign sa_sel_o = m0_sel_i;
+ assign sa_dat_o = m0_dat_i;
+ assign sa_we_o = m0_we_i;
+ assign sa_cyc_o = m0_cyc_i;
+ assign sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];
- assign s11_adr_o = m0_adr_i;
- assign s11_sel_o = m0_sel_i;
- assign s11_dat_o = m0_dat_i;
- assign s11_we_o = m0_we_i;
- assign s11_cyc_o = m0_cyc_i;
- assign s11_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];
+ assign sb_adr_o = m0_adr_i;
+ assign sb_sel_o = m0_sel_i;
+ assign sb_dat_o = m0_dat_i;
+ assign sb_we_o = m0_we_i;
+ assign sb_cyc_o = m0_cyc_i;
+ assign sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];
- assign s12_adr_o = m0_adr_i;
- assign s12_sel_o = m0_sel_i;
- assign s12_dat_o = m0_dat_i;
- assign s12_we_o = m0_we_i;
- assign s12_cyc_o = m0_cyc_i;
- assign s12_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];
+ assign sc_adr_o = m0_adr_i;
+ assign sc_sel_o = m0_sel_i;
+ assign sc_dat_o = m0_dat_i;
+ assign sc_we_o = m0_we_i;
+ assign sc_cyc_o = m0_cyc_i;
+ assign sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];
- assign s13_adr_o = m0_adr_i;
- assign s13_sel_o = m0_sel_i;
- assign s13_dat_o = m0_dat_i;
- assign s13_we_o = m0_we_i;
- assign s13_cyc_o = m0_cyc_i;
- assign s13_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];
+ assign sd_adr_o = m0_adr_i;
+ assign sd_sel_o = m0_sel_i;
+ assign sd_dat_o = m0_dat_i;
+ assign sd_we_o = m0_we_i;
+ assign sd_cyc_o = m0_cyc_i;
+ assign sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];
- assign s14_adr_o = m0_adr_i;
- assign s14_sel_o = m0_sel_i;
- assign s14_dat_o = m0_dat_i;
- assign s14_we_o = m0_we_i;
- assign s14_cyc_o = m0_cyc_i;
- assign s14_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];
+ assign se_adr_o = m0_adr_i;
+ assign se_sel_o = m0_sel_i;
+ assign se_dat_o = m0_dat_i;
+ assign se_we_o = m0_we_i;
+ assign se_cyc_o = m0_cyc_i;
+ assign se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];
- assign s15_adr_o = m0_adr_i;
- assign s15_sel_o = m0_sel_i;
- assign s15_dat_o = m0_dat_i;
- assign s15_we_o = m0_we_i;
- assign s15_cyc_o = m0_cyc_i;
- assign s15_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];
+ assign sf_adr_o = m0_adr_i;
+ assign sf_sel_o = m0_sel_i;
+ assign sf_dat_o = m0_dat_i;
+ assign sf_we_o = m0_we_i;
+ assign sf_cyc_o = m0_cyc_i;
+ assign sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];
// Address decode logic
// WARNING -- must make sure these are mutually exclusive!
- assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
- assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
- assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s2_addr);
- assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s3_addr);
- assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s4_addr);
- assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s5_addr);
- assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s6_addr);
- assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s7_addr);
- assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s8_addr);
- assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s9_addr);
- assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s10_addr);
- assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s11_addr);
- assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s12_addr);
- assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s13_addr);
- assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s14_addr);
- assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s15_addr);
-
+
+
+ assign ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask);
+ assign ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask);
+ assign ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask);
+ assign ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask);
+ assign ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask);
+ assign ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask);
+ assign ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask);
+ assign ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask);
+ assign ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask);
+ assign ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask);
+ assign ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask);
+ assign ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask);
+ assign ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask);
+ assign ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask);
+ assign ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask);
+ assign ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask);
+
+/*
+ assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr);
+ assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr);
+ assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr);
+ assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr);
+ assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr);
+ assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr);
+ assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr);
+ assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr);
+ assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr);
+ assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr);
+ assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr);
+ assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr);
+ assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr);
+ assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr);
+ assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr);
+ assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr);
+ */
endmodule // wb_1master
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-17 10:43:08 +0000