1 files changed, 2 insertions, 2 deletions
diff --git a/control_lib/setting_reg.v b/control_lib/setting_reg.v
index ccbaa3d2e..c8aff230f 100644
--- a/control_lib/setting_reg.v
+++ b/control_lib/setting_reg.v
@@ -1,14 +1,14 @@
 
 
 module setting_reg
-  #(parameter my_addr = 0)
+  #(parameter my_addr = 0, parameter at_reset=32'd0)
     (input clk, input rst, input strobe, input wire [7:0] addr,
      input wire [31:0] in, output reg [31:0] out, output reg changed);
    
    always @(posedge clk)
      if(rst)
        begin
-	  out <= 32'd0;
+	  out <= at_reset;
 	  changed <= 1'b0;
        end
      else