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-rw-r--r--control_lib/newfifo/.gitignore1
-rw-r--r--control_lib/newfifo/fifo18_to_ll8.v58
-rw-r--r--control_lib/newfifo/fifo36_to_ll8.v2
-rw-r--r--control_lib/newfifo/fifo_2clock.v61
-rw-r--r--control_lib/newfifo/fifo_2clock_casc.v31
-rw-r--r--control_lib/newfifo/fifo_2clock_cascade.v35
-rw-r--r--control_lib/newfifo/fifo_new_tb.v158
-rw-r--r--control_lib/newfifo/fifo_tb.v257
-rw-r--r--control_lib/newfifo/ll8_shortfifo.v13
9 files changed, 236 insertions, 380 deletions
diff --git a/control_lib/newfifo/.gitignore b/control_lib/newfifo/.gitignore
new file mode 100644
index 000000000..cba7efc8e
--- /dev/null
+++ b/control_lib/newfifo/.gitignore
@@ -0,0 +1 @@
+a.out
diff --git a/control_lib/newfifo/fifo18_to_ll8.v b/control_lib/newfifo/fifo18_to_ll8.v
deleted file mode 100644
index 4653244ef..000000000
--- a/control_lib/newfifo/fifo18_to_ll8.v
+++ /dev/null
@@ -1,58 +0,0 @@
-
-module fifo18_to_ll8
- (input clk, input reset, input clear,
- input [35:0] f18_data,
- input f18_src_rdy_i,
- output f18_dst_rdy_o,
-
- output reg [7:0] ll_data,
- output ll_sof_n,
- output ll_eof_n,
- output ll_src_rdy_n,
- input ll_dst_rdy_n);
-
- wire ll_sof, ll_eof, ll_src_rdy;
- assign ll_sof_n = ~ll_sof;
- assign ll_eof_n = ~ll_eof;
- assign ll_src_rdy_n = ~ll_src_rdy;
- wire ll_dst_rdy = ~ll_dst_rdy_n;
-
- wire f18_sof = f18_data[32];
- wire f18_eof = f18_data[33];
- wire f18_occ = f18_data[35:34];
- wire advance, end_early;
- reg [1:0] state;
- assign debug = {29'b0,state};
-
- always @(posedge clk)
- if(reset)
- state <= 0;
- else
- if(advance)
- if(ll_eof)
- state <= 0;
- else
- state <= state + 1;
-
- always @*
- case(state)
- 0 : ll_data = f18_data[31:24];
- 1 : ll_data = f18_data[23:16];
- 2 : ll_data = f18_data[15:8];
- 3 : ll_data = f18_data[7:0];
- default : ll_data = f18_data[31:24];
- endcase // case (state)
-
- assign ll_sof = (state==0) & f18_sof;
- assign ll_eof = f18_eof & (((state==0)&(f18_occ==1)) |
- ((state==1)&(f18_occ==2)) |
- ((state==2)&(f18_occ==3)) |
- (state==3));
-
- assign ll_src_rdy = f18_src_rdy_i;
-
- assign advance = ll_src_rdy & ll_dst_rdy;
- assign f18_dst_rdy_o = advance & ((state==3)|ll_eof);
- assign debug = state;
-
-endmodule // ll8_to_fifo36
diff --git a/control_lib/newfifo/fifo36_to_ll8.v b/control_lib/newfifo/fifo36_to_ll8.v
index 1befb9e6e..0dee1dfc6 100644
--- a/control_lib/newfifo/fifo36_to_ll8.v
+++ b/control_lib/newfifo/fifo36_to_ll8.v
@@ -1,6 +1,6 @@
module fifo36_to_ll8
- (input clk, reset,
+ (input clk, input reset, input clear,
input [35:0] f36_data,
input f36_src_rdy_i,
output f36_dst_rdy_o,
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 6b1eb607e..07ae090f2 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -1,9 +1,58 @@
+// FIXME ignores the AWIDTH (fifo size) parameter
+
module fifo_2clock
- #(parameter DWIDTH=32, AWIDTH=9)
- (input wclk, input [DWIDTH-1:0] datain, input write, output full, output reg [AWIDTH-1:0] level_wclk,
- input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output reg [AWIDTH-1:0] level_rclk,
- input arst);
+ #(parameter WIDTH=36, SIZE=6)
+ (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+ input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+ input arst);
+
+ wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels
+ wire full, empty, write, read;
+
+ assign dst_rdy_o = ~full;
+ assign src_rdy_o = ~empty;
+ assign write = src_rdy_i & dst_rdy_o;
+ assign read = src_rdy_o & dst_rdy_i;
+
+ generate
+ if(WIDTH==36)
+ if(SIZE==9)
+ fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if(SIZE==11)
+ fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if(SIZE==6)
+ fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else
+ fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ else if((WIDTH==19)|(WIDTH==18))
+ if(SIZE==4)
+ fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
+ (.rst(rst),
+ .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ endgenerate
+
+ assign occupied = {{(16-SIZE-1){1'b0}},level_rclk};
+ assign space = ((1<<SIZE)+1)-level_wclk;
+
+endmodule // fifo_2clock
+
+/*
+`else
+ // ISE sucks, so the following doesn't work properly
reg [AWIDTH-1:0] wr_addr, rd_addr;
wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
@@ -62,5 +111,7 @@ module fifo_2clock
level_wclk <= wr_addr - rd_addr_wclk;
always @(posedge rclk)
level_rclk <= wr_addr_rclk - rd_addr;
-
+`endif
endmodule // fifo_2clock
+
+*/
diff --git a/control_lib/newfifo/fifo_2clock_casc.v b/control_lib/newfifo/fifo_2clock_casc.v
deleted file mode 100644
index e9b0cfc25..000000000
--- a/control_lib/newfifo/fifo_2clock_casc.v
+++ /dev/null
@@ -1,31 +0,0 @@
-
-module fifo_2clock_casc
- #(parameter DWIDTH=32, AWIDTH=9)
- (input wclk, input [DWIDTH-1:0] datain, input write, output full, output [AWIDTH-1:0] level_wclk,
- input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output [AWIDTH-1:0] level_rclk,
- input arst);
-
- wire full_int, empty_int, full_int2, empty_int2, transfer, transfer2;
- wire [DWIDTH-1:0] data_int, data_int2;
-
- shortfifo #(.WIDTH(DWIDTH)) shortfifo
- (.clk(wclk), .rst(arst), .clear(0),
- .datain(datain), .write(write), .full(full),
- .dataout(data_int), .read(transfer), .empty(empty_int) );
-
- assign transfer = ~full_int & ~empty_int;
-
- fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
- (.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int), .level_wclk(level_wclk),
- .rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2), .level_rclk(level_rclk),
- .arst(arst) );
-
- assign transfer2 = ~full_int2 & ~empty_int2;
-
- shortfifo #(.WIDTH(DWIDTH)) shortfifo2
- (.clk(rclk), .rst(arst), .clear(0),
- .datain(data_int2), .write(transfer2), .full(full_int2),
- .dataout(dataout), .read(read), .empty(empty) );
-
-endmodule // fifo_2clock_casc
-
diff --git a/control_lib/newfifo/fifo_2clock_cascade.v b/control_lib/newfifo/fifo_2clock_cascade.v
new file mode 100644
index 000000000..5ce726977
--- /dev/null
+++ b/control_lib/newfifo/fifo_2clock_cascade.v
@@ -0,0 +1,35 @@
+
+module fifo_2clock_cascade
+ #(parameter WIDTH=32, SIZE=9)
+ (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+ input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+ input arst);
+
+ wire [WIDTH-1:0] data_int1, data_int2;
+ wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+ wire [SIZE-1:0] level_wclk, level_rclk;
+ wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied;
+ wire [15:0] l_space, l_occupied;
+
+ fifo_short #(.WIDTH(WIDTH)) shortfifo
+ (.clk(wclk), .reset(arst), .clear(0),
+ .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
+ .space(s1_space), .occupied(s1_occupied) );
+
+ fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
+ (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
+ .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
+ .arst(arst) );
+
+ fifo_short #(.WIDTH(WIDTH)) shortfifo2
+ (.clk(rclk), .reset(arst), .clear(0),
+ .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
+ .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+ .space(s2_space), .occupied(s2_occupied));
+
+ // Be conservative -- Only advertise space from input side of fifo, occupied from output side
+ assign space = {11'b0,s1_space} + l_space;
+ assign occupied = {11'b0,s2_occupied} + l_occupied;
+
+endmodule // fifo_2clock_cascade
diff --git a/control_lib/newfifo/fifo_new_tb.v b/control_lib/newfifo/fifo_new_tb.v
deleted file mode 100644
index f561df7fa..000000000
--- a/control_lib/newfifo/fifo_new_tb.v
+++ /dev/null
@@ -1,158 +0,0 @@
-module fifo_new_tb();
-
- reg clk = 0;
- reg rst = 1;
- reg clear = 0;
- initial #1000 rst = 0;
- always #50 clk = ~clk;
-
- reg [31:0] f36_data = 0;
- reg [1:0] f36_occ = 0;
- reg f36_sof = 0, f36_eof = 0;
-
- wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
- reg src_rdy_f36i = 0;
- wire dst_rdy_f36i;
-
- wire [35:0] f36_out, f36_out2;
- wire src_rdy_f36o;
- reg dst_rdy_f36o = 0;
-
- //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
- //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
-
- wire i1_sr, i1_dr;
- wire i2_sr, i2_dr;
- wire i3_sr, i3_dr;
- reg i4_dr = 0;
- wire i4_sr;
-
- wire [35:0] i1, i4;
- wire [18:0] i2, i3;
-
- wire [7:0] ll_data;
- wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
-
- fifo_short #(.WIDTH(36)) fifo_short1
- (.clk(clk),.reset(rst),.clear(clear),
- .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
- .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
-
- fifo36_to_fifo19 fifo36_to_fifo19
- (.clk(clk),.reset(rst),.clear(clear),
- .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
- .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
-
- fifo19_to_ll8 fifo19_to_ll8
- (.clk(clk),.reset(rst),.clear(clear),
- .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
- .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
- .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
-
- ll8_to_fifo19 ll8_to_fifo19
- (.clk(clk),.reset(rst),.clear(clear),
- .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
- .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
- .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
-
- fifo19_to_fifo36 fifo19_to_fifo36
- (.clk(clk),.reset(rst),.clear(clear),
- .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
- .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
-
- task ReadFromFIFO36;
- begin
- $display("Read from FIFO36");
- #1 i4_dr <= 1;
- while(1)
- begin
- while(~i4_sr)
- @(posedge clk);
- $display("Read: %h",i4);
- @(posedge clk);
- end
- end
- endtask // ReadFromFIFO36
-
- reg [15:0] count;
- task PutPacketInFIFO36;
- input [31:0] data_start;
- input [31:0] data_len;
- begin
- count <= 4;
- src_rdy_f36i <= 1;
- f36_data <= data_start;
- f36_sof <= 1;
- f36_eof <= 0;
- f36_occ <= 0;
-
- $display("Put Packet in FIFO36");
- while(~dst_rdy_f36i)
- @(posedge clk);
- @(posedge clk);
- $display("PPI_FIFO36: Entered First Line");
- f36_sof <= 0;
- while(count+4 < data_len)
- begin
- f36_data <= f36_data + 32'h01010101;
- count <= count + 4;
- while(~dst_rdy_f36i)
- @(posedge clk);
- @(posedge clk);
- $display("PPI_FIFO36: Entered New Line");
- end
- f36_data <= f36_data + 32'h01010101;
- f36_eof <= 1;
- if(count + 4 == data_len)
- f36_occ <= 0;
- else if(count + 3 == data_len)
- f36_occ <= 3;
- else if(count + 2 == data_len)
- f36_occ <= 2;
- else
- f36_occ <= 1;
- while(~dst_rdy_f36i)
- @(posedge clk);
- @(posedge clk);
- f36_occ <= 0;
- f36_eof <= 0;
- f36_data <= 0;
- src_rdy_f36i <= 0;
- $display("PPI_FIFO36: Entered Last Line");
- end
- endtask // PutPacketInFIFO36
-
- initial $dumpfile("fifo_new_tb.vcd");
- initial $dumpvars(0,fifo_new_tb);
-
- initial
- begin
- @(negedge rst);
- //#10000;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- ReadFromFIFO36;
- end
-
- initial
- begin
- @(negedge rst);
- @(posedge clk);
- @(posedge clk);
- PutPacketInFIFO36(32'hA0B0C0D0,12);
- @(posedge clk);
- @(posedge clk);
- #10000;
- @(posedge clk);
- PutPacketInFIFO36(32'hE0F0A0B0,36);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- end
-
- initial #20000 $finish;
-endmodule // longfifo_tb
diff --git a/control_lib/newfifo/fifo_tb.v b/control_lib/newfifo/fifo_tb.v
index 98fd63f8d..f561df7fa 100644
--- a/control_lib/newfifo/fifo_tb.v
+++ b/control_lib/newfifo/fifo_tb.v
@@ -1,155 +1,158 @@
-module fifo_tb();
+module fifo_new_tb();
- reg clk, rst;
- wire short_full, short_empty, long_full, long_empty;
- wire casc_full, casc_empty, casc2_full, casc2_empty;
- reg read, write;
-
- wire [7:0] short_do, long_do;
- wire [7:0] casc_do, casc2_do;
- reg [7:0] di;
-
- reg clear = 0;
-
- shortfifo #(.WIDTH(8)) shortfifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
- .read(read),.write(write),.full(short_full),.empty(short_empty));
+ reg clk = 0;
+ reg rst = 1;
+ reg clear = 0;
+ initial #1000 rst = 0;
+ always #50 clk = ~clk;
- longfifo #(.WIDTH(8), .SIZE(4)) longfifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
- .read(read),.write(write),.full(long_full),.empty(long_empty));
+ reg [31:0] f36_data = 0;
+ reg [1:0] f36_occ = 0;
+ reg f36_sof = 0, f36_eof = 0;
- cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
- (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
- .read(read),.write(write),.full(casc_full),.empty(casc_empty));
+ wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+ reg src_rdy_f36i = 0;
+ wire dst_rdy_f36i;
+
+ wire [35:0] f36_out, f36_out2;
+ wire src_rdy_f36o;
+ reg dst_rdy_f36o = 0;
- cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
- (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
- .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
+ //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+ //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+
+ wire i1_sr, i1_dr;
+ wire i2_sr, i2_dr;
+ wire i3_sr, i3_dr;
+ reg i4_dr = 0;
+ wire i4_sr;
+
+ wire [35:0] i1, i4;
+ wire [18:0] i2, i3;
- initial rst = 1;
- initial #1000 rst = 0;
- initial clk = 0;
- always #50 clk = ~clk;
+ wire [7:0] ll_data;
+ wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
- initial di = 8'hAE;
- initial read = 0;
- initial write = 0;
+ fifo_short #(.WIDTH(36)) fifo_short1
+ (.clk(clk),.reset(rst),.clear(clear),
+ .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+ .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
- always @(posedge clk)
- if(write)
- di <= di + 1;
-
- always @(posedge clk)
- begin
- if(short_full != long_full)
- $display("Error: FULL mismatch");
- if(short_empty != long_empty)
- $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)");
- if(read & (short_do != long_do))
- $display("Error: DATA mismatch");
- end
+ fifo36_to_fifo19 fifo36_to_fifo19
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
+ .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
+
+ fifo19_to_ll8 fifo19_to_ll8
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
+ .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+ .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
+
+ ll8_to_fifo19 ll8_to_fifo19
+ (.clk(clk),.reset(rst),.clear(clear),
+ .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+ .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
+ .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
+
+ fifo19_to_fifo36 fifo19_to_fifo36
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
+ .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
+
+ task ReadFromFIFO36;
+ begin
+ $display("Read from FIFO36");
+ #1 i4_dr <= 1;
+ while(1)
+ begin
+ while(~i4_sr)
+ @(posedge clk);
+ $display("Read: %h",i4);
+ @(posedge clk);
+ end
+ end
+ endtask // ReadFromFIFO36
+
+ reg [15:0] count;
+ task PutPacketInFIFO36;
+ input [31:0] data_start;
+ input [31:0] data_len;
+ begin
+ count <= 4;
+ src_rdy_f36i <= 1;
+ f36_data <= data_start;
+ f36_sof <= 1;
+ f36_eof <= 0;
+ f36_occ <= 0;
+
+ $display("Put Packet in FIFO36");
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ $display("PPI_FIFO36: Entered First Line");
+ f36_sof <= 0;
+ while(count+4 < data_len)
+ begin
+ f36_data <= f36_data + 32'h01010101;
+ count <= count + 4;
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ $display("PPI_FIFO36: Entered New Line");
+ end
+ f36_data <= f36_data + 32'h01010101;
+ f36_eof <= 1;
+ if(count + 4 == data_len)
+ f36_occ <= 0;
+ else if(count + 3 == data_len)
+ f36_occ <= 3;
+ else if(count + 2 == data_len)
+ f36_occ <= 2;
+ else
+ f36_occ <= 1;
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ f36_occ <= 0;
+ f36_eof <= 0;
+ f36_data <= 0;
+ src_rdy_f36i <= 0;
+ $display("PPI_FIFO36: Entered Last Line");
+ end
+ endtask // PutPacketInFIFO36
- initial $dumpfile("fifo_tb.vcd");
- initial $dumpvars(0,fifo_tb);
+ initial $dumpfile("fifo_new_tb.vcd");
+ initial $dumpvars(0,fifo_new_tb);
initial
begin
@(negedge rst);
- @(posedge clk);
- repeat (10)
- @(posedge clk);
- write <= 1;
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- @(posedge clk);
+ //#10000;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
+ ReadFromFIFO36;
+ end
+
+ initial
+ begin
+ @(negedge rst);
@(posedge clk);
@(posedge clk);
- read <= 1;
- @(posedge clk);
- read <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
-
- repeat(10)
- begin
- write <= 1;
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- read <= 1;
- @(posedge clk);
- read <= 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- end // repeat (10)
-
- write <= 1;
- repeat (4)
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- read <= 1;
- repeat (4)
- @(posedge clk);
- read <= 0;
- @(posedge clk);
-
-
- write <= 1;
- repeat (4)
- @(posedge clk);
- write <= 0;
+ PutPacketInFIFO36(32'hA0B0C0D0,12);
@(posedge clk);
- repeat (4)
- begin
- read <= 1;
- @(posedge clk);
- read <= 0;
- @(posedge clk);
- end
-
- write <= 1;
@(posedge clk);
+ #10000;
@(posedge clk);
+ PutPacketInFIFO36(32'hE0F0A0B0,36);
@(posedge clk);
@(posedge clk);
- read <= 1;
- repeat (5)
- @(posedge clk);
- write <= 0;
- @(posedge clk);
- @(posedge clk);
- read <= 0;
@(posedge clk);
-
- write <= 1;
- repeat (16)
- @(posedge clk);
- write <= 0;
@(posedge clk);
-
- read <= 1;
- repeat (16)
- @(posedge clk);
- read <= 0;
@(posedge clk);
-
- repeat (10)
- @(posedge clk);
- $finish;
end
+
+ initial #20000 $finish;
endmodule // longfifo_tb
diff --git a/control_lib/newfifo/ll8_shortfifo.v b/control_lib/newfifo/ll8_shortfifo.v
new file mode 100644
index 000000000..39ada9a4f
--- /dev/null
+++ b/control_lib/newfifo/ll8_shortfifo.v
@@ -0,0 +1,13 @@
+
+
+module ll8_shortfifo
+ (input clk, input reset, input clear,
+ input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o,
+ output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i);
+
+ fifo_short #(.WIDTH(11)) fifo_short
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+
+endmodule // ll8_shortfifo
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-18 10:29:48 +0000