diff options
Diffstat (limited to 'control_lib/newfifo')
| -rw-r--r-- | control_lib/newfifo/fifo18_to_ll8.v | 58 | ||||
| -rw-r--r-- | control_lib/newfifo/fifo_2clock.v | 42 |
2 files changed, 27 insertions, 73 deletions
diff --git a/control_lib/newfifo/fifo18_to_ll8.v b/control_lib/newfifo/fifo18_to_ll8.v deleted file mode 100644 index 4653244ef..000000000 --- a/control_lib/newfifo/fifo18_to_ll8.v +++ /dev/null @@ -1,58 +0,0 @@ - -module fifo18_to_ll8 - (input clk, input reset, input clear, - input [35:0] f18_data, - input f18_src_rdy_i, - output f18_dst_rdy_o, - - output reg [7:0] ll_data, - output ll_sof_n, - output ll_eof_n, - output ll_src_rdy_n, - input ll_dst_rdy_n); - - wire ll_sof, ll_eof, ll_src_rdy; - assign ll_sof_n = ~ll_sof; - assign ll_eof_n = ~ll_eof; - assign ll_src_rdy_n = ~ll_src_rdy; - wire ll_dst_rdy = ~ll_dst_rdy_n; - - wire f18_sof = f18_data[32]; - wire f18_eof = f18_data[33]; - wire f18_occ = f18_data[35:34]; - wire advance, end_early; - reg [1:0] state; - assign debug = {29'b0,state}; - - always @(posedge clk) - if(reset) - state <= 0; - else - if(advance) - if(ll_eof) - state <= 0; - else - state <= state + 1; - - always @* - case(state) - 0 : ll_data = f18_data[31:24]; - 1 : ll_data = f18_data[23:16]; - 2 : ll_data = f18_data[15:8]; - 3 : ll_data = f18_data[7:0]; - default : ll_data = f18_data[31:24]; - endcase // case (state) - - assign ll_sof = (state==0) & f18_sof; - assign ll_eof = f18_eof & (((state==0)&(f18_occ==1)) | - ((state==1)&(f18_occ==2)) | - ((state==2)&(f18_occ==3)) | - (state==3)); - - assign ll_src_rdy = f18_src_rdy_i; - - assign advance = ll_src_rdy & ll_dst_rdy; - assign f18_dst_rdy_o = advance & ((state==3)|ll_eof); - assign debug = state; - -endmodule // ll8_to_fifo36 diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v index 2ada39fb0..07ae090f2 100644 --- a/control_lib/newfifo/fifo_2clock.v +++ b/control_lib/newfifo/fifo_2clock.v @@ -16,21 +16,33 @@ module fifo_2clock assign read = src_rdy_o & dst_rdy_i; generate - if(SIZE==9) - fifo_xlnx_512x36_2clk mac_tx_fifo_2clk - (.rst(rst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if(SIZE==11) - fifo_xlnx_2Kx36_2clk mac_tx_fifo_2clk - (.rst(rst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if(SIZE==6) - fifo_xlnx_64x36_2clk mac_tx_fifo_2clk - (.rst(rst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + if(WIDTH==36) + if(SIZE==9) + fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==11) + fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==6) + fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else + fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==19)|(WIDTH==18)) + if(SIZE==4) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; |