5 files changed, 6 insertions, 6 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index 09b7e11f1..c1d6767d1 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -413,7 +413,7 @@ module u1plus_core
    // Readback mux 32 -- Slave #7
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd2}; //major, minor
+   localparam compat_num = {16'd9, 16'd3}; //major, minor
 
    wire [31:0] reg_test32;
 
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index ee27af939..a98e1de34 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -454,7 +454,7 @@ module u1e_core
    // Readback mux 32 -- Slave #7
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd0}; //major, minor
+   localparam compat_num = {16'd9, 16'd1}; //major, minor
 
    wire [31:0] reg_test32;
 
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 369f01183..abc32406e 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -436,8 +436,8 @@ module u2plus_core
    // Buffer Pool Status -- Slave #5   
    
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd0}; //major, minor
-   wire [31:0] churn = status; //tweak churn until timing meets!
+   localparam compat_num = {16'd9, 16'd1}; //major, minor
+   wire [31:0] churn = 0; //tweak churn until timing meets!
 
    wb_readback_mux buff_pool_status
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 6bf60fe58..93064254f 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -442,7 +442,7 @@ module u2_core
    // Buffer Pool Status -- Slave #5   
    
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd0}; //major, minor
+   localparam compat_num = {16'd9, 16'd1}; //major, minor
    wire [31:0] churn = 0; //tweak churn until timing meets!
 
    wb_readback_mux buff_pool_status
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index ca2f847bc..2788dc9d5 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -41,7 +41,7 @@ module vita_rx_chain
    wire clear;
    assign clear_o = clear;
    wire clear_int;
-   setting_reg #(.my_addr(BASE+3)) sr
+   setting_reg #(.my_addr(BASE+8)) sr
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(),.changed(clear_int));